FPGA state machine implementation of a simple sequential odd parity generator/checker

Thread Starter

smerf786

Joined Nov 22, 2011
3
In the past we had to create a AND-OR 3 bit parity generator/checker. But im not sure how to do the 7bit. I think I have to use MUX. How would I go about designing it? Do I need a truth table? Im kind of lost. I just need a sense of direction on how to go about doing this. He gave us a state diagram

Also this is the assignment

Experiment 7 - FPGA state machine implementation of a simple sequential odd parity generator/checker for a 7 bit memory

Design a state machine implementation of a simple sequential 7 bit odd parity generator/checker system that performs as follows.

Use a reset button (BTN0) to intialize the system such that the bits of data register R (R7-R0) and data register S (S7-S0) are 0 and all eight LEDs are initially unlit.

Pushbutton BTN1 is used to load one of the registers from switches SW7 - SW1 (LSB). The register to be loaded is selected using SW0. If SW0=0 when pushbutton BTN1 is pushed, then 7 data bits are loaded from switches SW7 - SW1 (LSB) to the corresponding bits of register R. If SW0=1 when pushbutton BTN1 is pushed, then 7 data bits are loaded from the switches to the corresponding bits of register S.

Pushbutton BTN2 is used to check parity for the register selected using SW0. If SW0=0, parity is checked for R. If SW0=1, parity is checked for S. When pushbutton BTN2 is pushed the parity for the selected register is generated using a sequential parity checker, and the parity bit is stored in bit 0 of the selected register. Once the parity check is complete, the contents of the register are displayed using LED7-LED0 corresponding to register bits 7 through 0, with the LED lit if the register data is a 1.

See the following file (Blackboard) for some examples of the types of Xilinx building blocks that might be useful in this experiment.

Xilinx mux, D flip flop, shift register components.pdf
 

Attachments

Papabravo

Joined Feb 24, 2006
14,698
Hint #1: You don't need an FSM to generate or check parity. It is a combinatorial circuit that can be implemented from any conveniently available gates.
Hint # 2: The inputs to your FSM are the buttons.
 

WBahn

Joined Mar 31, 2012
26,305
It appears that the intent is to do this sequentially where you are fed one bit at a time.

So imagine you are the processor and I tell you a 7 bit value but I give you just one bit at a time. You can write down whatever you want, but each time I give you a bit you can only use what you have written down previously plus the bit I've just given you. You want to write down as few things as possible.

Hint: You can do this by remembering just one bit of information.
 

WBahn

Joined Mar 31, 2012
26,305
If you are totally lost, meaning that you have absolutely no idea how to do any part of this assignment, then your first step is to get a drop slip from your school's registrar's office.

Otherwise, post your best effort at working YOUR assignment as far as you can.
 

Brownout

Joined Jan 10, 2012
2,390
You'll need to shift the bits in your register, and compare them to a value that represents the parity of your value that accumulates with each bit. Does that make sense? As an exercise, write out your data, make it anything, and the write out a shifted value and what the parity would be for each bit as it's shifted out and compared to the parity at the previously shifted bits. See if you can find a pattern.
 

WBahn

Joined Mar 31, 2012
26,305
A useful thing to do is to consider the following question:

I have given you the first 6 bits of a particular value already and now I tell you that the 7th (and final) bit is a 1. What is the essential piece of information you need to have remembered about those first six bits in order to determine the needed value of the parity bit.
 
Top