FPGA spartan3

Discussion in 'Embedded Systems and Microcontrollers' started by ecjohnny, Oct 26, 2012.

  1. ecjohnny

    Thread Starter Senior Member

    Jul 16, 2005
    hey anyone had experience in Xilinx Spartan-3A Evaluation Kit ? i am using this to test my vhdl program. The simulation run well for a toggle LED but does not run when i burn the .bit file on my spartan3A board. The constraint file mapping seem right. i am suspecting some clock issue, can anyone be kind and explain what the code below does? :


    rst_bar <= not rst;
    p0_out <= not p0_out_bar;
    p1_out <= not p1_out_bar;
    p2_out <= not p2_out_bar;
    p3_out <= not p3_out_bar;
    process (clk,clk_div,counter2)
    if( rst = '0' ) then
    counter2 <= (others => '0');
    clk_div <= '0';
    elsif clk='1' and clk'event then
    counter2 <= counter2+1;
    if counter2 = "111111111111111111" then
    clk_div <= not clk_div;
    end if;
    end if;
    end process;

    Anyone may have any suggestion that i might have got wrong? Thanks.
  2. tshuck

    Well-Known Member

    Oct 18, 2012
    This is a description of a clock divider, just gives you a lower frequency clock to reference.

    Have you configured your.ucf file? If not, go snoop around Xilinx for how to implement it.