Hi, How many output pins of FPGA can be used at once, and how much is the maximum curent drawan by the FPGA on general?
Thanks in advance.

 

I think that all i/o pins can be used at once, and the current drawn is very generally in the order of 100-300mA, but this depends on the configuration and clock frequency. Also I think that FPGAs have a large current spike on powerup.

 

I think that current estimate is optimistic. A couple of milliamps is more likely on a pin by pin basis. The whole chip may also have a power dissipation limit. That said, why would you ask a question like that in a forum, in preference to reading the datasheet. Do you have a clue about how many manufacturers and chip types there are out there? Get off your armchair and gather datasheets. That is the only true path to knowledge grasshopper.

 

I think that current estimate is optimistic. A couple of milliamps is more likely on a pin by pin basis.

I understood his question as power consumtion of an FPGA, not how much current you can draw from each pin. Each pin could allow something like 10-20mA, and like you said there is both max dissipation in the chip and max total current in power pins.

 

Thanks, I want max power being used in FPGA, cause I am developing testing system to analyse the transient response testing system for the voltage regulators for digital system. So, I want to set the limits of output current for my device..

 

Look here, http://www.actel.com/documents/UnderstandingFPGAPower.pdf, they say that the inrush current for sram devices is up to 1A.