Hi, I come from the background of microcontroller design. I am learning fpga design. Usually in the ucontrollers the total number of pwm is limited as per the vendors. In FPGA how can i determine the maximum number of pwm I can drive from a fpga. For example, currently i am working with microchips Smart fusion2 SOC. It has a microcontroller subsystem + fpga embedded in one chip. I would like to know the maximum number of pins I can drive PWM output pins.

Link

As per the link above, The total number of I/0 lines in TQ144 package is 84 lines, So does it mean I can use all the 84 pins as input and ouput pins ?

Thank you,
Ashok

 

Hi, I come from the background of microcontroller design. I am learning fpga design. Usually in the ucontrollers the total number of pwm is limited as per the vendors. In FPGA how can i determine the maximum number of pwm I can drive from a fpga. For example, currently i am working with microchips Smart fusion2 SOC. It has a microcontroller subsystem + fpga embedded in one chip. I would like to know the maximum number of pins I can drive PWM output pins.

Link

As per the link above, The total number of I/0 lines in TQ144 package is 84 lines, So does it mean I can use all the 84 pins as input and ouput pins ?

Thank you,
Ashok

In a FPGA
you are designing the silicon,
pin wise, to a first approximation, every pin is available as a PWM output,
they are what ever you design them to be , in put , out put, tri state, low speed, high speed, 3v3, 2v5 1v8 ,

its up to you

There are limits with every chip / design that you have to stay inside,
but they are also to a large extent up to your design,

A small for instance that might be relevant,
Most FPGAs have a "limit" on the maximum number of IO that can switch in the same direction at the exact same instance, due to ground bounce,
But for a PWM, that could be counteracted by phase shifting the different PWM outputs,

As an FPAG can easily clock at 100's of MHz,
then 10 ns phase shifting is really no problem,

 

In custom chips, on the other hand, it may be very difficult to get a fab house that will gaurantee a minimum delay and I knew of a case in which designs that used gate delays declined to bid on production, so the customer had to lie about the function of the stacked up inverters.

 

The total number of I/0 lines in TQ144 package is 84 lines, So does it mean I can use all the 84 pins as input and ouput pins ?

Yes you probably can use all 84 I/O pins.

maximum number of pwm I can drive from a fpga

You might need a pin for clock input and a reset pin. Some FPGAs have internal clocks. You might need some pins to talk to the FPGA. SPI or I2C bus.
Lets say that you have 80 PWMs in the FPGA. So they all turn on at the same time and each can turn off by what value is in a register. It is not a good idea to have all the I/O pins switch at the same time. I have made FPGAs with almost all pins used for PWM. I broke the PWMs into groups and shifted the groups so only 8 pins would switch at one time.

 

Just a note: You cannot get a more authoritative reply on this subject than the one above.

 

Re can you use all 84 pins as input / output

You need to look at the data sheet for your specific device.

Some pins might be pre configured as input or output only
some might be clock input only

Do some research on your particular chip.