# Floating solar panel voltage measurement

#### Veracohr

Joined Jan 3, 2011
764
I came across this circuit in a TI design guide for a MPPT charge controller (https://www.ti.com/lit/ug/tiduej8a/tiduej8a.pdf):

It says it's for "voltage sense of floating panels (disconnected via low-side panel enable)." I'm having trouble understanding how it's supposed to work when there's no DC connection between ground and the panel low side (P-). The full schematic of the design is here: https://www.ti.com/lit/pdf/tidryu8 and here is the section showing the panel connection:

How is the measurement circuit going to produce a current from P+ to ground when there's no DC connection between P- and ground? I tried simulating the measurement circuit along with the high value capacitors and a load resistor to ground in place of the controller circuits that are powered by the panel:

The simulation showed a large current from the source, through the large capacitance (charge transfer), and through the FET's source-drain diode to return to the source. This enabled a current through the PNP of the voltage measurement circuit, but it was much too high and resulted in saturation of the PNP with a 12V collector voltage, whereas the document says it should be less than 3.3V for the MCU ADC.

They state this circuit is supposed to enable voltage measurement of the panel when the low side is disconnected from ground, but I don't see how that could be so when the source (panel) and measurement circuit don't share a ground. Any thoughts?

#### ronsimpson

Joined Oct 7, 2019
2,007
If the panel was totally floating it could not work.
Voltage P+ to P- is divided by 2 via R1,3. This voltage -0.65V is across R2. Current flows from P+ through R2 into R4 and produces a voltage about 1/10 as much. This circuit only works if there is some connection from Panel to ground. I see the connection now. P+ through R39 to the capacitor bank sitting on ground.

#### michael8

Joined Jan 11, 2015
278
In #1 the simulation is missing the PNP emitter resistor which sets the current through it (based on the base voltage).

However, I'm a bit mystified at the TI circuit. It appears to me that Q4 the CSD18540 nfet is connected
backwards and it's internal diode will always connect the panel negative to ground, it can never block.

Since the nfet can't really turn the panel off the PNP voltage transfer circuit "works". I'd agree with Veracohr
that this doesn't look right.

The PNP base and emitter are connected reasonably and base current will flow (from the panel), however
the collector current has nowhere to go if the solar panel were to be really disconnected. With an output load
on the whole circuit things might differ, but I'd not use such a circuit.

full TI schematic (on many pages): https://www.ti.com/lit/pdf/tidryu8

floatpv1 is a simulation with the Q4 netf as TI describes it.

floatpv2 is a simulation with the Q4 nfet turned around so it can really block current flow.

The panel voltage sense output in simulation of floatpv2 is negative...

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#### ronsimpson

Joined Oct 7, 2019
2,007

#### michael8

Joined Jan 11, 2015
278
ronsimpson I'm not sure what you are saying in #4? How about some text?

#### ronsimpson

Joined Oct 7, 2019
2,007

#### Veracohr

Joined Jan 3, 2011
764
I thought I was going crazy for a minute. When I simulated the circuit yesterday (at home) I was getting a huge DC current through the capacitor. Today I simulated it again (at work, so I re-created it), and it only had no DC current through the capacitor.

Turns out I had accidentally put in 0.1Ω of parallel resistance, when it was supposed to be series. Whoops. Also whoops on forgetting the emitter resistor. Now I see it working, although it still has the load current of the control circuit going through the FET body diode. The design guide for the circuit has board images, and I can see that Q4 is indeed connected as shown in the schematic, with the drain connected to P-. Maybe it's a low enough current when the panel is disconnected that they decided it was fine.

#### michael8

Joined Jan 11, 2015
278
As I see it, there isn't any case where "the panel isn't connected". With Q4s drain going to the panel
negative it can't block current from the solar panel as Q4s internal diode will conduct. If they are blocking current
from the solar panel it's elsewhere in their circuit. They could have the microprocess turn Q6/Q7 (main switching
high side nfets) off to block current from the solar panel positive lead. I don't really see a purpose for Q4.