Not so long ago decided to carry out quite new project based on dynamic split/join of processor cores . Idea is that core splits into small cores with lower bits range as program code processed and back. The idea is that program average data bit range is much lower than max 64 or 128 bits of processor width. So it gives opportunity to avoid problems in splitting programs into 2 core or 4 cores. Increase processing of data and instructions.
Drawback is that there are a lot of new lines for core regulating signals and dependent consequent calculations. Possible problem is that one device should be controlled on the data overflow exception.
Problems occured with proper parametrisation of all possible combinations.
Still thinking of model / language/architecture to choose. I had chosen JOP processor for that.
Want to know what others are thinking?
Drawback is that there are a lot of new lines for core regulating signals and dependent consequent calculations. Possible problem is that one device should be controlled on the data overflow exception.
Problems occured with proper parametrisation of all possible combinations.
Still thinking of model / language/architecture to choose. I had chosen JOP processor for that.
Want to know what others are thinking?