Hey, I have to design a logic counter that can produce a one hertz clock from a 4MHz source on the software package Quartus. I have read loads on this but cant seem to understand the basic logic of this. I have been using D-Type Flip Flops and "and" gates. If i could understand the logic behind it properly I believe i could design the circuit. Any help on flip flops and how they are used in these cases would be really helpful. Thanks Lisa
Some thoughts which might help you; You need to divide by four which is the same as dividing by two twice (yes?). To divide by two you can use a flip-flop which changes state on a rising (or falling) edge. (rise 1=output high, rise 2 = output low, rise 3 = output high, etc) You can see how that effectively divides the number of pulses by 2. For more on flip-flops check out http://en.wikipedia.org/wiki/Flip-flop_(electronics) (edited to correct faulty link)
If you look up decimal counters, you will see that by applying the oscillator to the input of one, it's output will effectively divide the input frequency by 10. Cascsade 6, and the frequency will be down to 4 Hz. two flip flops and the 1 Hz signal is produced. I don't know what logic family you are proposing to use, so I can't suggest the IC's.
Oopsie! I misread the OP as having to get 1 MHz from 4 MHz. Okay, so we need to divide by 4000000 rather than by 4. Different problem. One way of doing this would be to first divide by four and then six times by 10 which is easy enough. Another way is to have a straight binary counter which is reset when it gets to 4000000. 4000000 requires 22 bits in binary so you would need a 22 bit binary counter. Then with gates you detect the 7 bits which indicate the count and use that to generate a pulse which resets the counter to zero. This has the advantage that you can easily divide by any number and even adjust the number with switches. I have used this approach in order to use odd crystals as time base for frequency counters etc.
Guys -- Quartus is a software package from Altera that allows you to design with really huge gate arrays. A 22 stage counter probably won't even use 1/10 of one percent of an EP2C8Q208C8 let alone a fraction of the 208 pins. Must be nice to have an embarassemnt of riches, so to speak. ROFL -- Ahhh....cha..cha..cha
This makes no sense. As you point out it is overkill. It would only make sense as an exercise in learning and practicing with that particular device. Also, I assume the OP is looking for learning about basic ways to deal with this specific problem and others like it. I would think that solving the problem in the simplest and most elegant ways would add points while solving it with a Rube Goldberg machine would detract points.
Do not interpret anything I said in this regard as impugning any of your answers. I was only trying to add my observation on the use of the particular software package, and by inference the environment that the OP was working in. Clearly some us us may have thought he was looking at an implementation in discrete chips. BTW the Quartus package is a 680Mb download. Biggest one I've ever had to wait for on a high speed link. Took almost an hour. Makes you long for the 1200 baud Hayes modem and the early days of the BBS's
Speaking of "the old days," I remember hooking up some JK flip-flops, LEDs, and a switch on a solderless breadboard. After playing with the circuit, I had a real feel for "flip-flopping" and why switches should be debounced! --Rich
If you take two T Flip Flops, 0 and 1. Set T to 1. Connect Clock to T-FF0. Connect Q0 to clock of T-FF1. Q1 will be the period of the clock times 2. You can hook up more T-FF in a sequence to get a longer period.