Hello,

I got a problem related to D-Flip Flops, here's the problem;

I. Problem 1:​

a) Design and implement a D Flip-Flop using AND, OR, and NOT gates.
b) Draw the truth table for the inputs (Q(t), D, CLK), gate outputs (AND, OR) and outputs (Q(t+1), Q’(t+1) ).​

Ok, so the first part is easy, I guess. Say I got this D-Flip-Flop;

I'll just use NOT gates at the end of each gate, and that will solve a. That's correct, right?​

Now, I have problems with part b.​

The truth table for inputs (Q(t), D, CLK). Uh, how can I put CLK on the truth table? And the Gate Outputs (AND, OR)? I really don't know. What I have is;​

Can someone explain me how to put the Gate Outputs, and CLK on a truth table, please? For Q'(t+1) it would be something like (1, 0, 1, 0) right?​

Any help is gladly appreciated.​

 

Why not get the datasheet for a 7474 flip flop? It should have a diagram of the internal logic. Not to mention a truth table.

Yours does not have any means of latching the state after the clock. A flip flop should maintain its state until a new clock pulse changes it.

 

Hi..

With your logic diagram.

Start one step at a time.

You know that your 2 NOR gates cross coupled produces a bistable latch.

You know that Q follows Data. and "Q (NOT Q) follows NOT data.

so you start your logic dia. with your bistable latch. (2 NOR gates)
lable your outputs as you have done.

step 2. Now Data input AND the clk input will = a Q output (high).

now draw up that logic sequence (using gates) to your latch.

step 3. Now NOT data input AND clk. input will = a "Q output. (high)

now draw that into your logic diag.

Make 2 of thes drawings. one for each input state.

Then carefully using colored pencils red for (high) and green for (low)

trace your diag. for each input and output states.

 

apply kanaugh map you will find forbidden sates. solution reset them at start up vcc res.cap to conditon the states otherwise the chicken becomes the egg.