Hello, I got a problem related to D-Flip Flops, here's the problem; I. Problem 1: a) Design and implement a D Flip-Flop using AND, OR, and NOT gates. b) Draw the truth table for the inputs (Q(t), D, CLK), gate outputs (AND, OR) and outputs (Q(t+1), Q(t+1) ). Ok, so the first part is easy, I guess. Say I got this D-Flip-Flop; I'll just use NOT gates at the end of each gate, and that will solve a. That's correct, right? Now, I have problems with part b. The truth table for inputs (Q(t), D, CLK). Uh, how can I put CLK on the truth table? And the Gate Outputs (AND, OR)? I really don't know. What I have is; Can someone explain me how to put the Gate Outputs, and CLK on a truth table, please? For Q'(t+1) it would be something like (1, 0, 1, 0) right? Any help is gladly appreciated.