I need to understand how can i wire J-K flip-flops to produce a binary up count at their Q outputs. Also, what is the advantage of a D-type Flip flop when comparing it to the SR flip flops. i have a test and i really need to understand this. Thanks

 

Post a sketch of your effort so far at finding a solution. We can then make suggestions on where you may need help.

In the meantime you will likely benefit from consulting a datasheet on a typical J/K flip-flop. In particular study the published truth table.

hgmjr

 

Here is what i have done so far.

 

Your clock input to the 7476 goes to a pullup resistor. I don't think that will work. If J4 is left as a short, U1A may get a bit hot.

What are the NAND gate SR flip flops supposed to demonstrate?

 

i put the J/K on the bottom left, but my question is how can i wire J-K flip flops to produce a binary up count at their Q outputs... i am completely lost i wouldn't know how to explain this ... my test is tomorrow and this question was in the review sheet :}

 

What would a binary up count look like on paper? How could you arrange for more than one J-K to produce that output? Hint - one flip flop isn't enough to make a counter.

With J-K flip flops, the state of J & K determine the output on being clocked. D flip flop's outputs follow the D input when clocked. There is a data sheet available for 7476's and for 7474's - use a search engine to find them. The data sheets give all the details about how the devices work.

 

How about that:
http://www.allaboutcircuits.com/vol_4/chpt_11/2.html

As for the SR question, there really isn't an SR Flip Flop. There is an SR latch and JK, D and T FFs.

 

thanks alot