Flip Flop

Discussion in 'General Electronics Chat' started by shyam, Oct 24, 2005.

  1. shyam

    Thread Starter New Member

    Sep 12, 2005
    I need to know on how to avoid metastability in flip flops,
  2. n9352527

    AAC Fanatic!

    Oct 14, 2005
    Metastability can not be avoided completely, instead flip flop can be designed so that the probability of metastability occuring is rare enough (high MTBF). In simple cases it can be sufficiently avoided by observing the setup and hold time, but this is not always possible if the input signals are asynchronous. Instead the flip flop can be designed with shorter setup and hold time to reduce the metastable probability. Connecting two or more flip flops in series can also reduce the probability of metastability occuring.
  3. nanobyte

    Senior Member

    May 26, 2004
    What is metastability? Why does it occur? Does it only occur in flip flops?
  4. n9352527

    AAC Fanatic!

    Oct 14, 2005
    metastability is the state where a circuit hover between stable states (in metastable state) for an indefinite amount of time. In other words that circuit can't decide which state to go into in response to input signal(s). Given sufficient time it might decide to go into one of the stable state, but the waiting time can not be guaranteed.

    It occurs on many different types of circuits, such as interfaces between two different frequencies clocked logic, many asynchronous circuits or generally where the interfaces to input signals are asynchronous, etc..

    In flip flops it occurs mainly if the input signal occurs temporally close to the clock signal or it held its state for a shorter time than necessary, i.e. setup and hold time violations.

    Metastability is a quite involved subject. If you are interested you can search for more materials on the web or find a good digital design textbook.
  5. Dave

    Retired Moderator

    Nov 17, 2003