# Finite State Machines - Moore/Mealy Diagrams for Verilog

#### stupidlogic

Joined Aug 10, 2010
39
I need to create a finite state machine in Verilog. It's kind of like a mod-10 counter, but with some variations.

When,
w1w0 = 00 the count remains the same
w1w0 = 01 the count increases by one
w1w0 = 10 the count increases by two
w1w0 = 11 the count decreases by one

And then obviously, I want to display the counter on a 7-seg display.

Before I start to do the Verilog stuff, I want to make a state diagram that describes this machine. My textbook doesn't help me very much and I don't understand how to create transition, state, and state/output tables for the machine.

Can anyone give me some suggestions on where to start or some good resources to learn more about it? I'm working on it now and will post what I have later this evening, but I'm struggling here. Thank you in advance.

#### stupidlogic

Joined Aug 10, 2010
39
Maybe it was easier than I thought. I think I have one worked out if anyone cares to comment about its correctness. And I haven't looked at the Verilog portion yet, but I'm sure I could use some pointers with that as this will pretty much be my first FSM in Verilog. Thanks for the help! #### stupidlogic

Joined Aug 10, 2010
39
Here is my code and I'd like to hear some feedback. I haven't been able to test it on a board yet but does anyone see any problems with it? Thank you.

Rich (BB code):
/*
Finite State Machine
- Four input types: Stays, counts up by one,
counts up by two, and counts down by one
*/

module FSM_partIV (SW,KEY,HEX0);
input [2:0]SW;
input [0:0]KEY;
output [6:0]HEX0;

parameter n = 4;

reg [n-1:0]state_reg,next_state;

wire Clk,Resetn;
wire [1:0]W;
wire [n-1:0]Z;

assign Clk = KEY;
assign Resetn = SW;
assign W = SW[2:1];

// state declaration
parameter zero = 4'b0000;
parameter one = 4'b0001;
parameter two = 4'b0010;
parameter three = 4'b0011;
parameter four = 4'b0100;
parameter five = 4'b0101;
parameter six = 4'b0110;
parameter seven = 4'b0111;
parameter eight = 4'b1000;
parameter nine = 4'b1001;

// state register
always @(posedge Clk or nededge Resetn)
if(Resetn == 0)
state_reg <= zero;
else
state_reg <= next_state;

// next state logic
always @(state_reg or W)
case (state_reg)
zero:
if (W == 00)
next_state = zero;
else if (W == 01)
next_state = one;
else if (W == 10)
next_state = two;
else if (W == 11)
next_state = nine;
else
next_state = zero;
one:
if (W == 00)
next_state = one;
else if (W == 01)
next_state = two;
else if (W == 10)
next_state = three;
else if (W == 11)
next_state = zero;
else
next_state = zero;
two:
if (W == 00)
next_state = two;
else if (W == 01)
next_state = three;
else if (W == 10)
next_state = four;
else if (W == 11)
next_state = one;
else
next_state = zero;
three:
if (W == 00)
next_state = three;
else if (W == 01)
next_state = four;
else if (W == 10)
next_state = five;
else if (W == 11)
next_state = two;
else
next_state = zero;
four:
if (W == 00)
next_state = four;
else if (W == 01)
next_state = five;
else if (W == 10)
next_state = six;
else if (W == 11)
next_state = three;
else
next_state = zero;
five:
if (W == 00)
next_state = five;
else if (W == 01)
next_state = six;
else if (W == 10)
next_state = seven;
else if (W == 11)
next_state = four;
else
next_state = zero;
six:
if (W == 00)
next_state = six;
else if (W == 01)
next_state = seven;
else if (W == 10)
next_state = eight;
else if (W == 11)
next_state = five;
else
next_state = zero;
seven:
if (W == 00)
next_state = seven:
else if (W == 01)
next_state = eight:
else if (W == 10)
next_state = nine:
else if (W == 11)
next_state = six;
else
next_state = zero;
eight:
if (W == 00)
next_state = eight;
else if (W == 01)
next_state = nine;
else if (W == 10)
next_state = zero;
else if (W == 11)
next_state = seven;
else
next_state = zero;
nine:
if (W == 00)
next_state = nine;
else if (W == 01)
next_state = zero;
else if (W == 10)
next_state = one;
else if (W == 11)
next_state = eight;
else
next_state = zero;
default:
next_state = zero;
endcase

assign Z = next_state;

// implement 7-segment decoder
hex_7seg H0 (Z,HEX0);

endmodule