Here is my attempt to find fan-out for TTL inverter circuit.





As you can see, I did analysis for high input (low output) and used condition for saturation of output transistor Q3 to find max. number of gates which can be connected.
When input signal is low, output will be high, aprox. Vout = Vcc - Vd2 - Vbe4. Which condition should I use to find max. number of gates which can be connected in this case?

 

Well, what defines when the output is no longer valid according to the spec?

 

Voh_min? (minimum output voltage for logic high)

 

Btw please check my work, I think it is ok but I need confirmation

 

Voh_min? (minimum output voltage for logic high)

That's one criterion. There are three more that have to be met over the entire spec'ed operating range of the device. Then there are numerous others. For instance, there is a spec on the max/min rise/fall times. If the fanout causes it to fail to meet that spec, then the maximum fanout is less than that used.

 

Well, I don't think they want me to know all possible details about internal circuitry of logic gate I follow Digital electronics course and right now we learn how TTL gates work. I'm familiar with different parameters of gate including rise time and fall time. We didn't use rise time and fall time when calculating fan-out.

 

If the output is at "low" the next gate should "read low" at his input (maximum input voltage level to still be considered a low VIL).
Hence, Q3 saturation voltage should be less than VIL. So, Ic3 > Ie1' --->fan-out = Ic3/Ie1'

 

If the output is at "low" the next gate should "read low" at his input (maximum input voltage level to still be considered a low VIL).
Hence, Q3 saturation voltage should be less than VIL. So, Ic3 > Ie1' --->fan-out = Ic3/Ie1'

That's what I got: Ic3/Ie1' = Bf*Ib3/Ie1'
I put expressions for Ib3 and Ie1' and I get max. number of gates which can be driven.

 

Well, I don't think they want me to know all possible details about internal circuitry of logic gate I follow Digital electronics course and right now we learn how TTL gates work. I'm familiar with different parameters of gate including rise time and fall time. We didn't use rise time and fall time when calculating fan-out.

No, for an assignment like this you are probably only expected to look at the static voltages and currents.

You should have a set of specs for the particular TTL family for the max/min voltages and currents and what the thresholds are. Those define the box you are working with.