Explain charge injection in simple terms

Thread Starter


Joined Feb 13, 2012
Hi guys,

It's me again, I am hope to understand the term Charge Injection, I don't need all the details, I am hoping to get some simple explanation of what cause it, and how to avoid it.

Please don't link me to academic definition, as you may guess, my brain is no good at processing those(I am not smart).

Last edited:


Joined Mar 14, 2008
Charge injection in MOS devices, when they are used as a switch, is due to the gate capacitance. When the gate voltage is changed to turn the switch on or off the movement of charges in the gate-source and gate-drain capacitance injects charge into or subtracts charge from the conduction channel (depending upon the gate polarity change). This then appears as a spike of voltage in the signal being carried by the MOSFET. Thus to minimize charge injection you want to use MOSFETs with the minimum feasible gate capacitance, which generally means the smallest MOSFET device that still has a low enough ON resistance for the signal being switched.


Joined Mar 31, 2012
And there are other ways to deal with it, as well.

As long as the node that the charge is injected onto is isolated, what goes on comes off when the gate is switched the other way. Also, you can have another matched FET placed to pull a comparable amount of charge off the node.

Another context for charge injection is charge injected into the substrate. Thus charge can then make its way to other circuits and provide a source of crosstalk between them.


Joined Mar 14, 2008
Originally Posted by WBahn
Also, you can have another matched FET placed to pull a comparable amount of charge off the node.
I am not sure if I understand this, can you show me with a circuit please?
CMOS analog switches do that. They use an N-MOSFET and a P-MOSFET in parallel to switch the signal. Since the N-MOSFET and the P-MOSFET use opposite polarity signals to turn on and off, the charge injection from one is cancelled by the opposite charge injection from the other, limited by how well the two gate capacitances match.