hi im new here.
i have this problem in my science class we are going to put this

design a 4 bit even counter design using jk flip-flop
(0,2,4,6,8,0 so on..)

the state are
0-0000
2-0010
4-0100
6-0110
8-1000

next state
2-0010
4-0100
6-0110
8-1000
0-0000

this is what i got from my k-map
Q0
Jo= 0 Ko=1 LSB
Q1
J1=Q0(bar) K1=1
Q2
J2=Q2 K2=Q2
Q3
J3=Q2 K3=1 MSB

i tried putting this on my breadboard but the output isn't right.
0110
0111
it keeps repeating on that sequence
I did something wrong but i don't know what it is i'm just 12.
can you tell me?

 

Learn to think outside the box.
Build a 3-bit counter. No need to include the LSB since it is always 0.

 

Actually, I'm impressed that you are doing this kind of stuff at your age. What grade are you in? 6th?

If you were asked to build a 3-bit counter that counted 0-1-2-3-4-0..., could you do that?

Getting back to the design you came up with. If you were given the circuit as you describe (the J and K logic for each JKFF), could you analyze it to determine what the sequence would be that would result?

You definitely got a mismatch between your logic and your breadboard. If you have J0=0 and K0=1, that should result in Q0 always being 0. So focus on that on your breadboard, first. Make sure that any preset/reset inputs are tied to logic levels that ensure that they are not asserted -- do NOT leave them floating! Then ensure that you are putting the 0 and 1 into the right inputs of the LSB flipflop.

Look into that and see what you find.

If you can, please post your actual schematic (a scanned, handdrawn schematic is fine).

 

here is my schematic i did

 

Let's think about that schematic a bit.

Notice that there is no connection between Q0/Q1 and Q2/Q3. That means that the state that Q2 and Q3 transistion to are not dependent in any way on the value of either Q0 or Q1. Is that consistent with your next-state table?

What will the inputs to the J and K inputs of Q2 and Q3 be if Q2 is LO? What will happen from that point on?

Do these JKFFs have asynchronous reset and preset inputs? If so, how are they connected?

 

i really don't quite understand..

i was able to make 0,2,4,6,0 using a 3 bit counter...

is it possible to make it to 8 using just 3 bit counters?

im really

 

Counting 0,2,4,6,0,... is the same as 0,1,2,3,0,...
For this you need a 2-bit counter plus one static output of 0.

Counting 0,2,4,6,8,0... is the same as 0,1,2,3,4,0,...
There are four unique states. Hence you need a 3-bit counter plus one static output of 0.

Focus on a 3-bit counter cycling 0,1,2,3,4,0,...

 

tnx..
i will give it try..

 

im really sorry but can you check my kmap?
im having trouble making this work on a breadboard i think ive done something wrong
but i dont know what.
Previous State

qa-qb-qc

=
0--0--0
0--0--1
0--1--0
0--1--1
1--0--0

Next State

qa qb qc

.
0--0--1
0--1--0
0--1--1
1--0--0
0--0--0
.

ja ka

.
0--0
0--x
0--x
0--x
x--1

jb kb

.
0--x
1--x
x--0
x--1
0--x

jc kc

.
1--x
x--1
1--x
x--1
x--0
KMAP
JA--(C)
(qAqB)0 0
00----0-1
01----0-x
11----x-x
10----x-x

JA=qB KA=1

JB--(qC)
(qAqB)0 1
00----0-1
01----x-x
11----x-x
10----0-x

JB=qC

KB--(C)-
(qAqB)0-1
00----x--x
01----0--1
11----x--x
10----x--x
KB=qC

JC--(C)
(qAqB)0-1
00----1-x
01----1-x
11----x-x
10----x-x
JC=1


KC--(qC)
(qAqB)0 1
00----x-1
01----x-x
11----x-x
10----0-x
Kc=qA(bar)

 

Sorry, I can't view Karnaugh maps that way.

Check out this discussion:

http://forum.allaboutcircuits.com/showthread.php?t=58572

 

Sorry, I can't view Karnaugh maps that way.

Check out this discussion:

http://forum.allaboutcircuits.com/showthread.php?t=58572

im very sorry but i can't get my head to get the values right
comes with being a kid i guess..

can you check if this will work for a 0,1,2,3,4,0 counter
im using a 74LS73AP IC if that helps

im still confused im a slow learner

 

i think this is it.. i did something wrong on my k-map and it seems my breadboard
keeps producing a positive charge on everything on my breadboard that is confusing confused:

here is the work I've done though

 

Note that the equation next to your OR gate doesn't match the way it is wired.

So let's see what behavior your schematic should produce.

Q3|Q2|Q1|Q0||J3|K3||J2|K2||J1|K1||J0|K0||Q3'|Q2'|Q1'|Q0'
0|0|0|0||0|1||0|0||1|1||0|1||0|0|1|0
0|0|1|0||0|1||1|1||1|1||0|1||0|1|0|0
0|1|0|0

Do you see how I am building up this table?

See if you can finish it.