Emitted Coupled Logic (ECL) AND/NAND?

Discussion in 'Homework Help' started by jean28, Mar 9, 2013.

  1. jean28

    Thread Starter Member

    Sep 5, 2012
    Hey guys. I have this homework where I have to simulate a circuit that implements an AND/NAND gate with Emitter Coupled Logic.

    As I'm sure most of you know, the OR/NOR gates are the gates that are created the most with ECL technology. I searched online and found the model in the picture attached, which is supposed to implement a NAND/AND. How do I know which values I should put to the reference voltages (VBB1, VBB2)? Does anyone know if this circuit does indeed work to make a NAND/AND? Also, don't I need to add a current source between VEE and the emitters?

  2. WBahn


    Mar 31, 2012
    Your schematic shows four separate current sources, so I would say that, yes, you need to include them.

    As for the bias voltages, my first guess (and it is not much more than that) is that you want to set them around midrange. They are not quite symmetric, so for optimal performance you probably want one of them a bit different than the other.

    Run some sims and explore!