Hello,

I've used a modified version of the following AGC circuit:

http://www.elecdesign.com/Articles/Index.c...&ArticleID=6272

I'm a bit rusty with my circuit analysis capabilities and am struggling to figure out how to determine the Output Resistance of this circuit.

Any help would be greatly appreciated!!

 

Hi iracc,

I examined the AGC circuit schematic. It appears that this circuit was designed with the intentions of using it to feed an audio amplifier since the output impedance is relatively high. With P1 set to provide the maximum output signal level, the dc output impedance is 10K. As P1 is adjusted for lower levels of output the dc impedance decreases.

[Worth noting is that the positive peak of the output signal is being clamped at a diode drop above ground by the base emitter junction of Q1. This means that the output level of 1.2V p-to-p will swing from 0.7 volts above ground to -0.5 volts below ground. Any subsequent audio amplifier stage will need to take this dc offset into account.] This comment turned out to be incorrect. See subsequent postings by rjenkins and myself for corrections. hgmjr 11/11/2005

We recently had a posting on clamping circuits. Your AGC circuit turns out to be an interesting example of an application of one. The clamping circuit in this case plays a key role in establishing the output signal level at the 1.2 volt p-to-p level.

Hope this is helpful.

hgmjr

 

I agree on the impedance, but not the offset..

Until the peak-to-peak output voltage is enough for the transistor base to draw current, the output will be centred around 0V.

As the transistor base starts to draw current with an increasing signal, the output bias will shifted slightly negative.

If I were building this, I'd also put a resistor directly in line with the transistor base to reduce any hard clipping, especially when the level increases rapidly. I'd try something like 1K.

An extra diode (1N914 or 1N4148 etc) across the transistor base & emitter (cathode to base) would both improve the effectiveness of the level control & remove the bit of DC offset.

 

Originally posted by rjenkins@Nov 10 2005, 06:37 PM
I agree on the impedance, but not the offset..

[post=11587]Quoted post[/post]​

Hi rjenkins,

I reviewed the circuit again in light of your comment and I have concluded that you are correct. There is negligible DC offset in the output of the AGC circuit throughout the designed input signal range of 0 to 20 volts.

My initial comment was based on the flawed assumption that Q1 was being driven into saturation. Instead it looks like Q1 operates for the most part in the linear region and so the base-emitter junction never quite reaches the full 0.7 volt forward voltage drop normally associated with a saturated transistor. Rather, the base-emitter junction must be reaching an equilibrium state at around 0.6 volts which when multiplied by 2 to arrive at the peak to peak value yields the 1.2 volts indicated in the schematic.

Good catch.

hgmjr

 

Hey guys,

Thanks alot for your comments! I appreciate it!

 

Oh boy...

I just realized that I didn't quite explain myself properly. I'm actually taking the output right at the output of the amplifier and not at the Potentiometer at the bottom... thus complicating the act of finding the resistance seen at the output.

The reason I'm taking it there is because I need a DC offset of around 0.8-1V and that is what I get at the amplifier output... unless someone can suggest a method of adding a DC offset at the potentiometer output.

Any comments on Ro or the DC Offset are appreciated.

Thanks!

 

Originally posted by iracc@Nov 16 2005, 03:39 AM
Oh boy...

I just realized that I didn't quite explain myself properly.  I'm actually taking the output right at the output of the amplifier and not at the Potentiometer at the bottom... thus complicating the act of finding the resistance seen at the output.

The reason I'm taking it there is because I need a DC offset of around 0.8-1V and that is what I get at the amplifier output... unless someone can suggest a method of adding a DC offset at the potentiometer output.

Any comments on Ro or the DC Offset are appreciated.

Thanks!

[post=11680]Quoted post[/post]​

The impedance at the output of the opamp (U1A pin 1) is very low. It is probably on the order of a few ohms provided the load that you are trying to drive with it does not demand more current from the opamp than is available. In other word, if the input impedance to the circuit being driven by the opamp's output is several kilo-ohms or greater, then I would expect the output of the opamp to remain unaffected by the load.

hgmjr