ECL Logic

Thread Starter


Joined Sep 18, 2007
Been reading Wiki but having some questions:

How does limiting base current in a differential amplifier avoid the saturation region? Is it because it prevents both b-e and b-c for being forward? If I'm limiting base current, why is it when in forward active the current is high enough to get current flowing through one leg vs. the other?

Also, why is saturation slow? I know I read that it's slow but why is it? Thanks!

Can someone help explain? Thanks!
Last edited:


Joined Mar 24, 2008
I'll give a shot, though it is probably inadequate. When you put a device into saturation you are radically overdriving it. It takes time to stop the overdriving and go into the linear mode, at which point conventional logic starts to start overdriving it in the other direction.

With a linear circuit you never leave this mode, and the slew rate is also very fast because -0.6 V is the high and -2.0V is the low. This low voltage amplitude switching means you don't have create a lot of energy just to create a fast edge.

Yet another aspect of this is if you look at ECL waveforms they are very rounded. This minimizes the RF energy floating around, and transfer between traces.

If you look really close at a ECL gate you will note it is really a differential amplifier, which is also used in high speed video amplifiers and other fast analog stuff.

ECL consumes gobs of current though, it is part of the trade off. Many of the telephone multiplexers and demultiplexers used for our light wave products in Alcatel were in the neighborhood of 40Gig or more. Generally one really high speed specialized chip fed another slightly slower specialized chip, until the frequency was in a manageable range. The faster the chip, the hotter it ran.


Joined Jul 31, 2011
How does limiting base current in a differential amplifier avoid the saturation region?
If you limit emitter current, then the collector-emitter voltage can be prevented from dropping to an excessively low value (assuming you have chosen a collector load resistor to appropriately match the emitter current).

Suppose, for a given collector load, you were to start increasing emitter current; Vce will start to decrease. If you were to allow Vce to drop below about a Vbe, you'd notice a steeply increasing collector-base capacitance. If you were then to further increase emitter current, Vce drops until saturation is reached - by this time Ccb is really large. If you wanted to turn the transistor off you'd need to get rid of all the charge on this capacitor, and this takes time (potentially a lot of time).

In TTL, the bottom output transistor's emitter is connected directly to ground. In order to turn it on satisfactorily, plenty of base current is provided, so that the transistor saturates (especially given that it hasn't a collector load resistor). When it comes to driving a logic '1', the transistor must be turned off as quickly as possible, and this involves the 'top' transistor 'dragging' the bottom transistor out of saturation - and you get spikes of commutation current as they fight each other. Use of a Schottky diode clamp to limit saturation much improves this situation.

As to how the differential pair operates, basically, the transistor whose base (and therefore emitter) is at the higher voltage robs current away from its partner, so that when it reaches half a logic swing higher, it has hogged virtually all the tail current: its collector will then be at a logic low, and its partner's will be at logic high (virtually at positive rail).

The reason ecl provides well-behaved transitions is that, in use, all interconnections have to be correctly terminated - so there are no reflections ("ringing" etc.). Coupled with the minimal logic swing, this tends to make ecl pretty quiet, in terms of generating unwanted noise.