doubts regarding clock frequency of 18f4550

Thread Starter


Joined May 29, 2013
i have doubt regarding oscillator frequency.
i am using 18f4550, XC8 compiler, primary oscillator of 20MHz. i have kept following configuration

Rich (BB code):
#pragma config PLLDIV = 5       // PLL Prescaler Selection bits (Divide by 5 (20 MHz oscillator input))
#pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])
#pragma config USBDIV = 2       // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes from the 96 MHz PLL divided by 2)

#pragma config FOSC = HSPLL_HS  // Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL))
#pragma config FCMEN = ON       // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)
#pragma config IESO = ON        // Internal/External Oscillator Switchover bit (Oscillator Switchover mode enabled)

#pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOR = SOFT       // Brown-out Reset Enable bits (Brown-out Reset enabled and controlled by software (SBOREN is enabled))
#pragma config BORV = 2         // Brown-out Reset Voltage bits ()
#pragma config VREGEN = ON      // USB Voltage Regulator Enable bit (USB voltage regulator enabled)

#pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

#pragma config CCP2MX = ON      // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
#pragma config LPT1OSC = OFF    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)
#pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)

#pragma config DEBUG = 1
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
#pragma config ICPRT = OFF      // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
so i am using oscillator mode as HSPLL for USB, and PLLDIV is 5 for derive 4MHZ frequency for PLL input for deriving 48 MHz clock.

I have confusion in system clock.
is following bits decide of system clock??
11 = 96 MHz PLL divided by 6 to derive system clock
10 = 96 MHz PLL divided by 4 to derive system clock
01 = 96 MHz PLL divided by 3 to derive system clock
00 = 96 MHz PLL divided by 2 to derive system clock

if yes then what is time for Machine cycle?

how to check frequency on which pic is running using pickit3 ??


Joined Feb 11, 2008
how to check frequency on which pic is running using pickit3 ??
A good method to find out what clock frequency the PIC is running at is to set TMR0 to 1:1 prescaler, and use this very simple code;
Rich (BB code):
TRISB = 0x00;  // portb is outputs
  if(TMR0L >= 128)  LATB = 0xFF;
  else              LATB = 0x00;
What that does is to output a frequency on the PORTB pins where the frequency is the instruction speed /256.

So if your clock speed is 48 MHz, inst speed is 12 MHz, and the freq output is 12MHz/256 = 46875 Hz.


Joined Jan 29, 2010
if yes then what is time for Machine cycle?
Look at this marked up clip from the datasheet.

The Basic CPU clock [refer image] is further divided internally to produce 4 machine timing periods.

So a 20MHz Xtal divided by 2 would give give a CPU clock of 10Mhz, this is always divided internally by 4, so an Instruction cycle would be 400nSec

To double check, use Roman's method.