Double buffered data latch - parallel input

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atferrari

Joined Jan 6, 2004
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In my design, every so many usec I output row/columns data (5 bytes x 8 bits ea) all at once. Up to now, I could go away with the 74HC595 serial shift register but since I need it to be faster, the time it takes to shift the 40 bits in and then show them all at once is more than what is available for each "frame".

Thinking of doing something similar with parallel input data latches strobing the 5-bytes output at once, I could not find an IC able to keep the previous value at the output UNTIL the 5 new ones are sequentially loaded.

Checked the 74HC373,374,573,574 variations but they all lack an intermediate register that would allow the succesive input of bytes while the previous data is still shown.

Any chip that I could have overlooked and is easily available? Even browsing the long list in the data books in paper in my library I couldn't find one.
 
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