In the first three entries of the truth table of a multiplexer whatever the value (0 or 1) of D0,D1,D2 it does not have any impact on the output because when the signals go through the AND gate the output of the it is 0 in the first three entries. Why am I wrong?
Let me explain with an example:
When D0 is 0, output (F) is equal to 0
When D0 is 1 still the output (F) is 0
So D0 is not equal to F (the output)
What am I missing here?
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Let me explain with an example:
When D0 is 0, output (F) is equal to 0
When D0 is 1 still the output (F) is 0
So D0 is not equal to F (the output)
What am I missing here?
Like
Comment
Share