I have ton ot good examples of BCD or decade counters but NONE have a "real" counter which can be loaded with arbitrary value just like the one depicted on the pix, which is a genetic SN74LS168 up/down ripple BCD counter with load?

Building it out of D flip-flops and ton of gates as the function diagram suggest is possible but will be a lot of Matlab work. I was curious whether someone had done it already and would be willing to share their .mdl file?

 

I'm missing a couple of things here. What exactly is a "real" counter, and why does Matlab have anything at all to do with the building of hardware for digital counters?

 

What exactly is a "real" counter, and why does Matlab have anything at all to do with the building of hardware for digital counters?

Given the OP mentions MDL-files, (I assume) this means the hardware model is implemented in Simulink rather than from within the core Matlab programme.

I have never done this in Simulink I cannot offer any constructive comments as to the initial query.

Dave

 

So does that mean the OP is looking for a "high-level" description of the finite state machine behavior of a "real" counter? If so that should be reasonably straightforward, but since I'm not familiar with the Simulink primitives its going to be a bit difficult for me to be of further assistance.

Like all FSMs you look at the inputs, wait for the clock edge, implement the behavior, generate the outputs and then do forever.

 

So does that mean the OP is looking for a "high-level" description of the finite state machine behavior of a "real" counter? If so that should be reasonably straightforward, but since I'm not familiar with the Simulink primitives its going to be a bit difficult for me to be of further assistance.

Like all FSMs you look at the inputs, wait for the clock edge, implement the behavior, generate the outputs and then do forever.

Within Simulink there is a a module known as Stateflow which allows you to define the state-flow characteristics for a FSM. The user specifies the state transition diagram including states and transition definitions. This then becomes a Simulink block that can be interfaces in the normal way. The stateflow block will accept inputs and give outputs of all typical data-types so it shouldn't be too difficult to adapt the FSM for a particular application. The big challenge is deriving the FSM diagram for the above counter.

Dave