Division on the last outputs in vhdl

Discussion in 'Embedded Systems and Microcontrollers' started by basmahassan, Feb 20, 2014.

  1. basmahassan

    Thread Starter New Member

    Feb 20, 2014
    hi all,
    counter count the number of input samples then the counter output (n) and i want to check if the numbers of samples is even do that (n*n) or if odd make that ((n*n)-1) will be something like that
    signal dis : integer range 0 to 255 := 0;
    signal n : integer range 0 to 255 :=0;
    if n mod 2=1 then
    n_of samples<= ((n*n)-1);
    n_of_samples <= n*n;
    end if;
    norm_dis <= dis / n_of_samples ;
    (dis) signal will have values as (1,6,9,8,.....100) and the second signal (n) will have values as (0,2,8,9.......,200) and i want to fetch the two last outputs from the two signal (100,200) and divide 100/200.how can i write it in vhdl and how can overcome the divide by zero error.
    i want help plz.
  2. tshuck

    Well-Known Member

    Oct 18, 2012
  3. Brownout

    Well-Known Member

    Jan 10, 2012
    1) Why are you posting this in off-topic?
    2) Why don't you use code tags for your code?
    3) Why don't you delineate comments?
    4) Why don't you tell us if this is supposed to be synthesized code?
    5) Why don't you explain the purpose of this code?

    I'd love to help, but I have no clue what you're talking aobut.