hi , i have this project using Xilinix spartan 3e kit , but i have a very limited knowlege of VHDL (just the basics) so anybody can point me in the right direction and any help of where to start is appreciated .

The project is to implement a “clock with stopwatch” using VHDL with the following specifications:
- The user should be able to reset the system by an external reset switch such that the clock restarts from 00:00:00 am and the stopwatch resets to 00:00:00.
- The user should be able to pause the “stopwatch” at any given time then resume from where it stopped.
- The “stopwatch” can be reset independently from the clock.
- All the outputs of the system [both the clock and the stopwatch] should be displayed on the FPGA LCD

thanks !!

Hey i'm from brazil and i'm trying so hard to do a clock with stopwatch, but i can't do it =( can you show me your project please ??

 

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