Hi all, I'm new to the forums but plan to become a regular member (just now discovered this forum; I'm excited!) Anyway, I'm an electronics engineering undergraduate student at the University of North Texas. I'm taking a class called Digital Logic and we have a semester project. We use Altera Quartus II software. The problem statement is this:

"Using state machine design, input two BCD numbers from switches (on the Altera DE2 board we use), add the two numbers and display the result on the seven segment display. A reset button restarts the state machine to the beginning. Incorporate a state machine that advances states based on a momentary push-button switch input. Test the inputs for validity and display E for error if a non-valid BCD number is entered."

Now I understand the material well, but we've never had a problem like this. Typically the labs are fairly simple and include in depth guidelines. The instructor and TAs are not able to help us; its driving me crazy! Thought I'd take a shot in the dark and see if anyone could help me. Thanks guys!

~Donny

 

Were you planning to do a schematic or were you planning to use VHDL or some other method of design entry?

 

The problem statement calls for using VHDL, but I have a better understanding of block diagram schematics. Once I have the problem correctly operating using a block diagram schematic, I think I can implement it using VHDL. I'm just not very good with VHDL. My professor hasn't taught it that well, and I haven't had many labs that require it. My main problem is just where to start. I have the BCD to seven segment decoder part down because we had to make the macro from VHDL code in a previous lab. I'm mainly stuck on how many inputs (I know I need clock and reset), and how to setup the adder circuit. And thank you for the quick response!

 

An input register to sample the switches would be a good idea.

The BCD adder should be straight forward. Start with a binary adder. Write a logic function for an invalid result. An invalid result is a member of the set {1010, 1011, 1100, 1101, 1110, 1111}. You need to do something with the result if an invalid digit is produced. Otherwise you should be set to go.

What are you using for a VHDL language reference?

 

I have my text book as a reference for the VHDL code, and my professors powerpoint notes offer some sample VHDL codes. And thanks for the help!

 

There are some interesting web resources for VHDL which you can find with the following Google searches.

1. VHDL Tutorial
2. VHDL Reference
3. VHDL Example

Good Luck

 

Try the free VHDL Cookbook (links directly to the PDF file).

Furthermore, West and Harris give a solid treatment of implementing state-machines using VHDL in their CMOS VLSI book. Once you have a state diagram, writing VHDL for the state-machine is actually pretty straightforward.

Dave

 

Now I'm having trouble creating a state machine design. I'm used to the state machine design progressing to the next state in order, but it seems like with this problem, each state could progress to any other state.. Also, I have no clue how to use state machine design when inputing two sets of BCD numbers.

 

At this stage of the design the numeric coding of the states and how the transitions are ordered is COMPLETELY irrelevant.

First make it work
Then make it fast
Then make it elegant.

If it were me I'd have a signal that said "Load Inputs". If that input is high then I'd load the inputs into the input register. As long as the inputs are not changing it doesn't matter if you load the register multiple times. If it's really important to load the inputs only once then build that into your state machine so that after you have loaded the inputs you inhibit the "Load Inputs" input from having any further effect.

When you get all done with the abstract design, then it will be time to assign numeric values to the states, and the transitions.