Hey all,
I have a problem...
Can sb pls explain me the performance of a clock signal? I know that it has high and low level and going from low to high and vice versa.
The problem is that how it is related to a digital circuit?
For example,
Can a clock signal be an input to an OR gate? Then if this is possible, since the clock is mostly edge triggered which means that only the transition time is important , how the clock affects the output of the OR gate?
An other question is that what is really left and right shifting?
Left means omitting one bit from the left side and adding a zero to the right side? right? but sometimes we just add a zero to the right side and don't omit any bit from left side? how come?
any help and explanation greatly appreciated...
I have a problem...
Can sb pls explain me the performance of a clock signal? I know that it has high and low level and going from low to high and vice versa.
The problem is that how it is related to a digital circuit?
For example,
Can a clock signal be an input to an OR gate? Then if this is possible, since the clock is mostly edge triggered which means that only the transition time is important , how the clock affects the output of the OR gate?
An other question is that what is really left and right shifting?
Left means omitting one bit from the left side and adding a zero to the right side? right? but sometimes we just add a zero to the right side and don't omit any bit from left side? how come?
any help and explanation greatly appreciated...