# Digital Logic and Clock

Discussion in 'Embedded Systems and Microcontrollers' started by sasan, Oct 31, 2010.

1. ### sasan Thread Starter New Member

Oct 31, 2010
4
0
Hey all,

I have a problem...

Can sb pls explain me the performance of a clock signal? I know that it has high and low level and going from low to high and vice versa.

The problem is that how it is related to a digital circuit?

For example,

Can a clock signal be an input to an OR gate? Then if this is possible, since the clock is mostly edge triggered which means that only the transition time is important , how the clock affects the output of the OR gate?

An other question is that what is really left and right shifting?

Left means omitting one bit from the left side and adding a zero to the right side? right? but sometimes we just add a zero to the right side and don't omit any bit from left side? how come?

any help and explanation greatly appreciated...

2. ### beenthere Retired Moderator

Apr 20, 2004
15,815
290
Here is what Wikipedia has to say about a clock signal - http://en.wikipedia.org/wiki/Clock_signal

Of course a clock can be applied to an OR gate, as long as the signal transitions satisfy the OR gate's input requirement. The OR gate should be high while the clock signal is high.

Get the data sheet for a 74194. That is a bidirectional shift register. The truth table will show you how it works.

3. ### sasan Thread Starter New Member

Oct 31, 2010
4
0
Thanks beenthere...

I 've got Wikipedia before, but I do not well understand how it would be when both a clock signal and also an data input enter an OR gate...

During the transion of clock pulse, it is neither 1 nor 0...so what clock value is considered for OR gate operation?
Further in shifting, whether left or right, during each clock transition we would have one bit shifting..right?

Any idea also about my question regarding shifting in the earlier post?

4. ### beenthere Retired Moderator

Apr 20, 2004
15,815
290
Any signal that satisfies the input requirement of a logic gate will be valid. The level will be sensed as low if below some threshold, and high if above another one.

There is no special property of an OR gate that makes it sense logic signals differently from any other type of gate. The only difference between a clock signal and any logic signal is that the clock runs at some frequency.

Transitions are significant in logic inputs that are not Schmitt triggers, where the voltage level is the significant component. For other logic inputs, any signal that transitions from one level to another quickly enough is treated as a valid input. There will be a period during the transition before the input senses the change from low to high or the reverse but, as long as the input specifications are satisfied, the output will respond to the input.

This is hard to understand. As above, what about an OR gate makes it differ from other gates? What do you mean by "clock value"?

Did you get that data sheet? Just Google "74194" to get it.

5. ### eblc1388 AAC Fanatic!

Nov 28, 2008
1,543
102
As the clock pulse level changes(rises) from 0 to 1, it will go through a certain voltage level in the middle between 0 and 1. For 5V logic, let's say this level is 2.5V.

Output of a CMOS OR gate, powered by a 5V supply, would probably becomes HIGH when one its inputs has a voltage of 2.5V or more.

So to answer your question, OR gate output stay low when clock is low, changes state during the clock edge when actual voltage is 2.5V and remains high when clock pulse is high.

The same applies with the clock trailing edge.

Not all IC families have input that changes the output state at 50% of the supply voltage. Check data sheet for actual level.

6. ### sasan Thread Starter New Member

Oct 31, 2010
4
0
Thanks beenthere and eblc1388.

I got the sheet and I am going through it.

Let me say, my problem comes from a sequential multiplier...

In this type of multiplication, the multiplier enters a right shift register and then it enters an inventer and then it enters an OR gate.
The other input of this OR gate is a clock signal...
So I can not understand what the output of OR gate would be?
This process is said to pick out each multiplier bit for multiplication process but I do not understand how come?

I try to put an image of the circuit to have more of your help.
Sorry if Make it confusing!

7. ### sasan Thread Starter New Member

Oct 31, 2010
4
0
i.e. Another problem is with a gate clock;
A control signal and a clock signal are both applied as inputs to an AND gate...
The operation is mainly done by control signal based on whether it is 1 or 0.
So this seems that the clock has no effect as we say oyput is 1 if control signal is 1 and 0 if control is 0. How come?

8. ### beenthere Retired Moderator

Apr 20, 2004
15,815
290
An OR gate will have a high output if either input is high.
Look at the truth table of an AND gate. The output is high only if both inputs are high at the same time.