Design a logic circuit of electronic lock with inputs P,Q,R so that output S is HIGH whenever Q=R. Using NAND gates.
P Q R S
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

I made the eq as : P' Q' R' +P ' Q R + P Q'R '+ PQR ... ' = compliment taking QR common
QR( P'+P) + Q'R'(P'+P)
QR + Q'R'

is this eq: correct?

 

If the output doesn't depend on one of the inputs, the simplified equation shouldn't have it, right?

Your truth table has some places where Q=R, yet S=0...

Edit: The OP has come back and modified the post, so the answer provided is not what was originally there....

 

If the output doesn't depend on one of the inputs, the simplified equation shouldn't have it, right?

Your truth table has some places where Q=R, yet S=0...

yes edited the post sorry about that are you talking about the P input? that it shouldn't be in the circuit?

 

yes edited the post sorry about that are you talking about the P input? that it shouldn't be in the circuit?

I'm saying that if the output is only dependent on Q and R, it stands to reason that the function that describes the output should only consist of Q and R, in a reduced form.

 

I'm saying that if the output is only dependent on Q and R, it stands to reason that the function that describes the output should only consist of Q and R, in a reduced form.

okay so if I only include Q and R in it so it will become with the equations as:

Q' R' + QR + Q' R' + QR

This will be the eq....

 

I'm not suggesting that you simply omit the P, but rather that, as a check, your final equation cannot have a P variable.

I would suggest either posting your K-map or Boolean algebraic steps so we can comment...

 

I'm not suggesting that you simply omit the P, but rather that, as a check, your final equation cannot have a P variable.

I would suggest either posting your K-map or Boolean algebraic steps so we can comment...

Got rid of the P in the final eq:
P' Q' R' +P ' Q R + P Q'R '+ PQR ... ' = compliment taking QR common
QR( P'+P) + Q'R'(P'+P)
QR + Q'R'

correct my truth table with the eq and the final eq is this correct? I'm trying to make the truth table will show you when it's done

 

Got rid of the P in the final eq:
P' Q' R' +P ' Q R + P Q'R '+ PQR ... ' = compliment taking QR common
QR( P'+P) + Q'R'(P'+P)
QR + Q'R'

correct my truth table with the eq and the final eq is this correct? I'm trying to make the truth table will show you when it's done

There you go.

You should learn to check your answers by comparing your simplified results against the original, that way, you needn't ask if you are right, but you'll know it.

 

There you go.

You should learn to check your answers by comparing your simplified results against the original, that way, you needn't ask if you are right, but you'll know it.

you mean to say that the eq that I got I should put the inputs and verify the results right? By the way made the circuit check it out please

http://postimg.org/image/tx0s7njqb/

 

you mean to say that the eq that I got I should put the inputs and verify the results right?

Precisely. If the functionality is any different, it is, by definition, not a simplified function. So, ensuring the same output for the same inputs will allow you to check the results yourself.

By the way made the circuit check it out please

http://postimg.org/image/tx0s7njqb/

Looks good.

Another way to check this is to map out the truth table (like above).

It is typically encouraged for you to upload images to this forum as links to other website will eventually break. You can do that by clicking the paperclip icon while posting.

 

I think the answer is true:

 

I think the answer is true:
[...]

Hi full,

While I'm sure you can do your own homework, doing other people's homework does not benefit them.

Please do not post answers as we try to teach people here and it's probably safe to reason the OP has seen many problems worked before. Showing the OP one more problem is unlikely to give them the clarity that comes from struggling through and grasping a problem one step at a time.

 

Hi full,

While I'm sure you can do your own homework, doing other people's homework does not benefit them.

Please do not post answers as we try to teach people here and it's probably safe to reason the OP has seen many problems worked before. Showing the OP one more problem is unlikely to give them the clarity that comes from struggling through and grasping a problem one step at a time.

ok ,I'm sorry,

I new in this forum

 

ok ,I'm sorry,

I new in this forum

No worries.

Just keep your answers to your threads.

 

Hi full,

While I'm sure you can do your own homework, doing other people's homework does not benefit them.

Please do not post answers as we try to teach people here and it's probably safe to reason the OP has seen many problems worked before. Showing the OP one more problem is unlikely to give them the clarity that comes from struggling through and grasping a problem one step at a time.

I had one more question in my mind that if I have got a circuit in which only AND gates have been used and I have to remake it using only NAND gates than for every one AND gate I have to use TWO NAND gates is that true?

 

I had one more question in my mind that if I have got a circuit in which only AND gates have been used and I have to remake it using only NAND gates than for every one AND gate I have to use TWO NAND gates is that true?

To implement the exact approach, yes, however, there are typically ways to reduce the logic and implement a complemented function to realize a smaller number of NAND gates than a 1 to 1 AND gate logic implementation.

In other words, reexamining the NAND gate version can usually reduce the number of gates used when converting to a NAND only implementation.