# digital design - state machines

Discussion in 'Homework Help' started by mccormick.cj, May 25, 2008.

1. ### mccormick.cj Thread Starter Member

May 25, 2008
10
0
Hi all, quick question

How do I come up with a schematic from only a state diagram or truth table?
I need to implement state diagrams using T, JK and/or D flip flops. How do I go about this after putting together a truth table?

Any help would be much appreciated

2. ### mik3 Senior Member

Feb 4, 2008
4,846
70
Do you want to implement the circuit form a truth table?

3. ### mccormick.cj Thread Starter Member

May 25, 2008
10
0
either a PS/NS table or a state diagram. I just need somewhere to start. My professor hasn't showed up in 2 classes but keeps assigning homework, so Im lost.

4. ### mik3 Senior Member

Feb 4, 2008
4,846
70
Well, i dont know what a PS/NS table is but if you explain me maybe i would be able to help you.

5. ### mccormick.cj Thread Starter Member

May 25, 2008
10
0
a previous state/ next state truth table

i attached the state diagram in question. Can you help me with that one?

File size:
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6. ### mik3 Senior Member

Feb 4, 2008
4,846
70
No, i am sorry i dont know how this work but you may find this website useful
http://en.wikipedia.org/wiki/State_transition_table

Also you can search in google for previous state/ next state truth table

7. ### Caveman Senior Member

Apr 15, 2008
471
1
So you need to create a table like this:
Code ( (Unknown Language)):
1.
2. IN LS NS
3.  0 00 10
4.  1 00 00
5.  0 01 11
6.  1 01 01
7.  0 10 01
8.  1 10 00
9.  0 11 00
10.  1 11 01
11.
So if each bit of the state variable (there are two) is a single flip flop, then you have on the output of the flip flop the last state (actually the current state) that you clocked to. The input will be the next state. It will be based on combinational logic using the last state and the input, so for next state bit 0 (the right one), you can see it will be a one if last state is 01 or last state is 10 and the input is 0 or if the last state is 11 and the input is 1. In equation form:

NS0 = LS1'*LS0 + LS1*LS0'*IN' + LS1*LS0*IN

You need to do this for both bits of the state. Now Z1 is based purely on state, so it is just a combinational value based on the output of the flip flops.
Z2 is a bit unclear, but it looks like it needs to be latched like a state. It's input is based on the next state logic above, the last state, and the input.

So the next Z2 value is needed. It is simply NZ2 = LS1*LS0*IN'. You would put NZ2 into the D input of a flip flop and the output would be the current Z2 value.

Does this make sense?

8. ### mccormick.cj Thread Starter Member

May 25, 2008
10
0
ok, so i get equations for each bit of my next state.

then how do i go from my equations to using a flip flop? so, how would i take these equations and use a T and JK flip flop in my schematic?

9. ### Caveman Senior Member

Apr 15, 2008
471
1
Start with using the idea of a D flip flop (which is what is usually used anyways), then alter it to use a T or JK flip flop for each. For a D flip flop, the state is the output, and the next state is the input. That way when the clock rising edge occurs, the state becomes the next state.

To use a T flip flop, you would have to drive the enable line correctly to make sure it toggles when it should. For a JK, you would have to drive two sets of logic, one for set, and one for reset.

10. ### mccormick.cj Thread Starter Member

May 25, 2008
10
0
alright. thanks alot, i appreciate the help