So I have a particular question in which I need to (possibly) modify the datapath and control of a simple architecture shown below:
I'm given the RTL saying this:
Z: RD1 <- RA - RB
(z is the flag from the previous instruction)
So seems pretty simple, I'm not sure if I have to add additional hardware or not to the architecture? I'm going to do the subtract operation only if Z has been asserted, but I'm not sure if or how to edit the datapath/control in order to get this working.
Thanks for any help
I'm given the RTL saying this:
Z: RD1 <- RA - RB
(z is the flag from the previous instruction)
So seems pretty simple, I'm not sure if I have to add additional hardware or not to the architecture? I'm going to do the subtract operation only if Z has been asserted, but I'm not sure if or how to edit the datapath/control in order to get this working.
Thanks for any help