digital design - Simple computer architecture

Thread Starter

Fear58

Joined Jan 11, 2010
9
So I have a particular question in which I need to (possibly) modify the datapath and control of a simple architecture shown below:



I'm given the RTL saying this:

Z: RD1 <- RA - RB

(z is the flag from the previous instruction)

So seems pretty simple, I'm not sure if I have to add additional hardware or not to the architecture? I'm going to do the subtract operation only if Z has been asserted, but I'm not sure if or how to edit the datapath/control in order to get this working.

Thanks for any help
 

nubelube

Joined Jan 3, 2010
16
Hint: What does the Branch Control do when Z is 0 but the branch instruction requires Z be 1 in order to take effect (that is, modify the PC register)?

One option would be to do the computation, but not write it to the destination register if Z is not asserted. You'll probably need some logic that uses info from the instruction decoder to only disable the register writeback when appropriate. (I haven't thought it through entirely, but...if for some reason your architecture is such that you need to write something to the register file, you might be able to do a "Write" that has no effect. e.g. If register R0 always returns 0, then it might be the case that you could write anything to R0 and the result is just discarded. If so, your logic could trigger changing the destination register to R0.)
 
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Thread Starter

Fear58

Joined Jan 11, 2010
9
Thanks nubelube, that was good guidance.
I ended up adding additional hardware and a control line from the instruction decoder. I utilized a flip flop storing Z's bit and put it through a mux that either selects RW or the output from the Z flip flop. This way, the instruction decoder can write to the destination register or not, like you kinda suggested with a ghost register?

Thanks man
 
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