Digital circuits

Thread Starter


Joined Mar 27, 2008
Hello everybody,

I am in a review course right now. It's a course that only meets one day a week, and we have a test on previous courses each of those days. Unfortunately, I was forced into taking one of those courses--digital circuits--at the same time as this course (as a co-req) if I wanted to keep my full time status. I am only half-way through my digital circuits course, but I have a test on the complete course on Monday in my review class. In other words, I am being tested on something I haven't learned yet.

So what I am asking for is a quick tutorial on a couple of practice questions. I have my answers written in bold. If they are wrong, please explain, or guide me to a web-page that can help. I don't ask for answers...only help. I hope those of you that recognize me know that.

Here are my worrisome questions:

1). A 1MHz signal is input to a counter. If the output of the final stage is 1kHz, what is the MOD of the counter?

a. 2 b. 10 c. 100 d. 1000

2.) A bit binary up/down counter is set to zero. If the DOWN counter mode is selected and a clock pulse applied, the counter value will be:

a. 0001 b.1111 c. 1000 d. 1110

3.) Many clocks and watches use a 32.768 Hz input signal. What is the modulus of the counter required to produce a 1 pulse/sec output?

a). 1 b). 256 c). 1024 d). 32,768 (I have no idea)

4). The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state of 11100100. After two clock pulses, the register contains:

a). 01011100 b). 10110101 c). 01111001 d). 00101101 (?)

I'll check shift registers on this site and others (if you have a recommendation, please post). The one I have had a hard time with is #3. Again, the answers won't help. I need to know how to solve. Any guidance would be great.



Joined Nov 17, 2003
In both the last two questions the answer is d.
I disagree mik3, Q4 is c):

Initial state: 11100100 where group 10110101 is serially shifted

After two clocks the LSBs of the initial register have dropped off and the remain bits have clocked two bits along. The LSBs of the group are serially shifted into the two MSBs of the register, i.e. 01111001.


Thread Starter


Joined Mar 27, 2008
Thanks for responding.

Dave, the shift register answer makes sense. Thanks.

Mik3, I don't understand why the answer is d).

Looking at flip-flop apps, frequency division by counting clock pulses has a pretty specific formula (i.e., for x flip-flops f(out) = f(in)/(2^x)).

Is there a specific way to determine f(out) for counters?