Hi guys,
I have a question with regards to a Digital reciever, which unfortunetly,I cannot post any info on (to avoid getting into trouble). It basically accepts a digital waveform and toggles the input data according.

I basically have one question. This reciever has two thresholds, Vhigh(ac) and vhigh(dc) ( and the same for the vlow), which are used to prevent the "ringing" of the input wave from the toggling the input data.

Is it common practice to have 2 different thresholds for toggling ? Like, I understand that the input waveform may have some noise, and that we wouldn't want the circuit to switch if the noise crosses our toggling threshold. So wouldn't we just have 1 threshold, and make it high enough ( or low enough ) such that the noise wouldn't cause it to switch ?

Thanks guys, I know i don't have much info .. unfortunelty I can't talk much :S so I appreciate anything you guys give me..

 

In 40+ years of doing this I've never heard of such a thing.

BTW I'm really curious about what kind of trouble you expect and from who. Waaasup?

 

Hi,

If this is a broadcast receiver, then the AC spec may apply to the signal at the several RF inputs, and the DC spec to the internal logic levels.

The input signal ringing is a wierd concept, though. Possibly that's more for multipath interference?

 

http://www.jedec.org/download/search/jesd8-8.pdf#search="SSTL 2"

Page 5 guys.... I don't understand that paragraph

 

Thanks for the link, I think I understand what's going on. At the dawn of time in the characterization of logic devices the "ac" thresholds were set at 10% and 90% of the signal level. These points on a waveform defined the timing parameters called "rise" time and "fall" time. Propagation delay was measured from the time the input changed until the corresponding output reached a certain value.

Instead of having those "ac" thresholds by convention, be a fixed percentage of the signal swing, they are now explicitly stated.

To review, the "dc" thresholds define the functional behavior of the device in terms of what is a one and a zero, while the "ac" thresholds define the points where the timing specs must be met.

I had to read the paragraph on the top of page five more than once, but I think I've got it now. Thanks for showing me something that I was not aware of.

 

No Problem .. As I like to say, you can learn something from everyone... even if they are less than (probably) half your age

Now, if these ac thresholds are simply the "10%" and "90%" values of the input waveform (for timing purposes), how does it help in terms of eliminating the affect of the ringing input toggling the data ? I still don't get it.

Thanks alot Papa, you've been of great help.

 

In SSTL receiver the AC threshold is specified as the timing marker for the input signal. The timing specifications and measurements are expressed in reference to the point where the input signal crossed the AC threshold. The DC threshold, meanwhile, is there to provide sufficient voltage margin to reject any unintended signal variation. As long as the ringing doesn't cross the DC threshold, then no logic transition would happen. This is how the DC threshold eliminates the effect of input ringing.

The AC thresholds in SSTL are not 10% and 90%, the specs have the correct levels referenced to VREF for both AC and DC thresholds.

 

....
The AC thresholds in SSTL are not 10% and 90%, the specs have the correct levels referenced to VREF for both AC and DC thresholds.

I never implied or stated that the "ac" thresholds were at 10% or 90%, but only that those values were used in other contexts. I did say that for this logic type that the voltage levels were explicitly stated.

There is nothing about these "ac" threshold that will do anything for you to help reduce ringing.

In early DRAM designs (ca. 1979-1983) I often put series resistors of 33 ohms in the address lines going to an array of DRAM chips. This increased the damping factor and cut down on the ringing. The chips were 16Kx1 and we had 64 of them on the board. You can see how this level of fanout creates inductance and capacitence. Doing this may or may not be acceptable with this logic type. I don't know for sure since I've never used it.

 

This is another SSTL standard used for VDDQ voltages of 1.8v... should be pretty much the same...

http://www.jedec.org/download/search/JESD8-15a.pdf


Page 2 states that the receiver will switch state when the input crosses the AC threshold ??? I'm totally confused...

 

You're getting hung up on the difference between an ideal logic device with no propagation delay and a real device that does have a delay characteristic. You need to look carefully at the timing diagrams to understand the phrases that are used.

Once the device passes the DC threshold the output is going to change. How fast it changes is measured from one point on the plot of voltage versus time to some other point on the plot of voltage versus time. Life was much simpler when the same point was used for everything.

 

That comment was intended for Mazaaq and not for you Papabravo. Sorry for the confusion.

The SSTL 18 works similarly with SSTL 3. You have to realise that the DC threshold is there to hold the logic steady once the input is in the specified level. The AC threshold still has a role in determining the entry criteria of the logic level. But once it is in, then it won't change again until the DC threshold is crossed. It is probably similar to a hysteresis with an extra threshold, if there is such a thing.

The paragraphs on both documents explain this, but in different words.