Hi,
Below is the differential ring oscillator .cir file. I am trying to design a ring oscillator with 2GHz oscillating frequency. Output is straight line at around 5V. Is it because I have not given initial condition? If yes, can I please get some help on how to set initial condition? I highly appreciate any help in evaluating the circuit


.MODEL NMOS1 NMOS (VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N)

*(each differential cell)
.SUBCKT DELAY 1 2 3 4 5 6
R1 5 3 20K
R2 4 5 20K
M1 3 1 6 6 NMOS1 W=3U L=1U
M2 4 2 6 6 NMOS1 W=3U L=1U
.ENDS DELAY

XC 1 2 3 4 5 6 DELAY
XD 4 3 7 8 5 6 DELAY
XE 8 7 1 2 5 6 DELAY


ISS 6 0 20U
VDD 5 0 5
.TRAN 1NS 1500NS
.PROBE
.END

 

What "output" is a straight line at 5V. I see a circuit wit eight numbered nodes. I don't see any indication of what node is considered the "output". We are not mind readers!

Isn't the whole idea behind a differential pair that you steer the current from a current source between two transistors? If so, then isn't it rather important that current not going through one transistor of a pair must go through the other?

I also don't think you are being consistent in how you are wiring up the stages.

 

Hi WBahn,

Thanks a lot for your reply. I have attached ckt figure (pdf).

Appreciate your guidance..pl ignore my naivete !

 

Where is the "ring" feedback?

 

Why do you have the emitters of all six transistors tied together?

Do you understand that the purpose of the current sources in a differential pair is that the current has to go through one or the other transistor? When you tied them together like this, the current can go through one or (one of the other five) transistors. That is NOT a differential PAIR.

 

Thanks for your replies; here's an improved version;

R3 and M20 bias the ckt at 20u current

M3 is baising transistor of the subckt, current in M3 is divided and goes into M1 and M2, the output is taken at node 3 and 4 and is fed into next subckt inversely.

Looking forward for your kind comments



.MODEL NMOS1 NMOS (VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N)

*each differential ckt

.SUBCKT DELAY 1 2 3 4 5
R1 5 3 20K
R2 5 4 20K
M1 3 1 6 6 NMOS1 W=5U L=1U
M2 4 2 6 6 NMOS1 W=5U L=1U
M3 6 20 0 0 NMOS1 W=10U L=1U
VGS 20 0 .89V
.ENDS DELAY

*3 stages
XC 1 2 3 4 5 DELAY
XD 4 3 7 8 5 DELAY
XE 8 7 1 2 5 DELAY

*biasing ckt
R3 5 20 .205M
M20 20 20 0 0 NMOS1 W=10U L=1U
VDD 5 0 5V

*analysis requests
.TRAN 1NS 1500NS
.PROBE
.END

 

And....what?

You have a biasing circuit that you then don't use.

You still have an inconsistency in how you wire the three stages to each other.

 

Hi WBahn,

thanks for sticking with me..i appreciate it.. here's the modified ckt:

*differential ring oscillator

.MODEL NMOS1 NMOS (VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N)

*each differential ckt

.SUBCKT DELAY 1 2 3 4 6 5
R1 5 3 20K
R2 5 4 20K
M1 3 1 6 6 NMOS1 W=5U L=1U
M2 4 2 6 6 NMOS1 W=5U L=1U
.ENDS DELAY

*three stages
XC 1 2 3 4 6 5 DELAY
XD 4 3 7 8 12 5 DELAY
XE 8 7 1 2 18 5 DELAY

*biasing transistor below each differential pair.. connected to biasing ckt via node 20

M3 6 20 0 0 NMOS1 W=10U L=1U
M6 12 20 0 0 NMOS1 W=10U L=1U
M9 18 20 0 0 NMOS1 W=10U L=1U


*biasing ckt

R3 5 20 .205M
M20 20 20 0 0 NMOS1 W=10U L=1U
VGS 20 0 .89V
VDD 5 0 5V

* analysis requests

.TRAN 1NS 1500NS
.IC V(1)=1 V(2)=-1 V(3)=-1 V(4)=1 V(7)=1 V(8)=-1
.PRINT DC V(1) V(2)
.PROBE
.END


still doesn't work!!

 

In general, just saying, "Still doesn't work!" doesn't help very much. HOW doesn't it work? What does it do or not do that it indicating that it isn't working? Remember, we are NOT mind readers.

In this case, you still have not addressed one of the issues I pointed out in my very first response; namely, you are not connecting your stages together consistently. You have three stages that form a ring. Why are you connecting one pair together in a way that is different from the other two pairs?

Also, you are taking a step backwards with your bias circuit. The idea is to split a current mirror into two pieces -- the programming half and the current source half. You put the programming half (called the bias generator) in the top circuit and, since the current source draws no current from the bias generator, you put separate copies of the current source half in each subcircuit. You do not need this magical mystery voltage source with a magical mystery output of 0.89V at all -- that's what the bias circuit is there for.

 

I finally got some oscillation I increased the gate voltage of the biasing amplifier...
This is the file that worked... I have attached the graph of one of the differential cells in the ring oscillator..

your comments please !

Thanks,
Meghana
.


*DIFFERENTIAL RING OSCILLATOR
.MODEL NMOS1 NMOS (VTO=0.70 KP=110U GAMMA=0.4 LAMBDA=0.04 PHI=0.7
+MJ=0.5 MJSW=0.38 CGBO=700P CGSO=220P CGDO=220P CJ=770U CJSW=380P
+LD=0.016U TOX=14N)
.SUBCKT DELAY 1 2 3 4 6 5
R1 5 3 20K
R2 5 4 20K
M1 3 1 6 6 NMOS1 W=10U L=1U
M2 4 2 6 6 NMOS1 W=10U L=1U
* M3 6 20 0 0 NMOS1 W=10U L=1U
* VGS 20 0 .89V
.ENDS DELAY
XC 1 2 3 4 6 5 DELAY
XD 4 3 7 8 12 5 DELAY
XE 8 7 1 2 18 5 DELAY
M3 6 20 0 0 NMOS1 W=10U L=1U
M6 12 20 0 0 NMOS1 W=10U L=1U
M9 18 20 0 0 NMOS1 W=10U L=1U
VGS 20 0 1.5V

R3 5 20 .205M
M20 20 20 0 0 NMOS1 W=10U L=1U
VDD 5 0 5V

.TRAN 1NS 1500NS
.IC V(1)=0.5 V(2)=-0.5 V(3)=-.5 V(4)=.5 V(7)=.5 V(8)=-.5
.PRINT DC V(1) V(2)
.op
.PROBE
.END


*.IC V(1)=1V V(2)=-1V V(4)=2 V(3)=-2 V(7)=-1 V(8)=1
*.PRINT TRAN V(1) V(2)
* .IC V(1)=2 V(2)=1 V(3)=-1 V(4)=-1 V(5)=1
* .PRINT TRAN V(1) V(2) V(3) V(4) V(5)