differences between open collector and voltage output

Thread Starter

pau

Joined Mar 29, 2007
6
please let me know the difference between open collector and voltage ouput
 

bloguetronica

Joined Apr 27, 2007
1,359
If you are asking about open colector outputs, I must say that in those the output voltage depends mainly on the voltage used to pull-up (with a pull-up resistor) or the voltage used in the circuit whose input is being sinked by the open colector output.
For example, if you have a TTL logic gate with a open collector output, and this is being pulled-up by a 10K resistor to positive 15V , you can see that the output values may vary from 0V to aprox. 15V.
Actually, open collector outputs are used when we want a typical TTL circuit that uses 5V, to drive a 15V powered circuit (imagine a CMOS circuit or a motor).
So, in open collector outputs, the output voltages are not defined. Normally logic levels in open colector outputs are refered as high impedance or low impedance. If low impedance means 0 or 1, it depends on how you use it.
 

beenthere

Joined Apr 20, 2004
15,808
Let me clarify a couple of points. The high impedance state is only possible with "three state" logic. High impedance in essence means that the logic output has been turned off, and the ic is invisible to the circuit.

Open collector logic was originally developed so multiple ic's could share the same electrical line - like multiple inputs onto a computer bus. Check the logic family to see what the maximum voltage is that can be on the pull-up resistor. Three state logic is much more common with busses today (open collector stuff has to have increasingly smaller pull-up resistors as the number of inputs grows, but the switching time gets slower as the load gets larger - not good for speed).

The voltage output ic has all the stuff it needs on the chip. The output will swing only as far as Vcc, and will have a definite limit on the load it can manage.
 

bloguetronica

Joined Apr 27, 2007
1,359
Let me clarify a couple of points. The high impedance state is only possible with "three state" logic. High impedance in essence means that the logic output has been turned off, and the ic is invisible to the circuit.

Open collector logic was originally developed so multiple ic's could share the same electrical line - like multiple inputs onto a computer bus. Check the logic family to see what the maximum voltage is that can be on the pull-up resistor. Three state logic is much more common with busses today (open collector stuff has to have increasingly smaller pull-up resistors as the number of inputs grows, but the switching time gets slower as the load gets larger - not good for speed).

The voltage output ic has all the stuff it needs on the chip. The output will swing only as far as Vcc, and will have a definite limit on the load it can manage.
No, open collector output are defined by the means of high impedance (when the output transistor is cut off) or low impedance (when the output transistor is saturated). If you are talking about tristate logic is different (in those high impedance is to input and low impedance is to output).
Nevertheless, you can only define logic levels by voltage if the output is driven by two transistors (output will have low impedance, sourcing or sinking actively, instead of sinking).
If you have doubts, see more about open collector outputs and what they are for.
 

pebe

Joined Oct 11, 2004
628
No, open collector output are defined by the means of high impedance (when the output transistor is cut off) or low impedance (when the output transistor is saturated).
I have not come across this definition before. As far as I am aware, 'open collector' means there is no internal connection to the collector. So if the (NPN) transistor is conducting, the collector pin is at logic '0'. If not, the pin is effectively open circuit.
If you are talking about tristate logic is different (in those high impedance is to input and low impedance is to output).
My understanding of tristate logiic is that the output pin has three states depending on how the internal source feeding it is connected.
1. High. When the pin is connected to the IC's +ve supply
2. Low. When the pin is connected to the IC's -ve supply
3. Open. When the pin is unconnected.
Nevertheless, you can only define logic levels by voltage if the output is driven by two transistors (output will have low impedance, sourcing or sinking actively, instead of sinking).
Irrespective of the output source, The logic level is '1' if the output pin is at V+, or '0' if at V-.
 

bloguetronica

Joined Apr 27, 2007
1,359
I have not come across this definition before. As far as I am aware, 'open collector' means there is no internal connection to the collector. So if the (NPN) transistor is conducting, the collector pin is at logic '0'. If not, the pin is effectively open circuit.
You arleady told yourself the answer. Conducting = low impedance, cutoff = high impedance. Remember that a open swich does have a very high impedance (or resistance, its almost the same in this case), but it has. So a transistor will have too.
More to add, if a logic signal is 0 or 1, it depends on your vision. In false logic, 0 is +5V and 1 is 0 volts. In datasheets, the logic values are defined in terms of high and low, or in the case of open collector outputs, high impedance or low impedance. I am telling you this because open collector outputs are more often used in a false logic context, for example, if they are sinking current from LEDs.
My understanding of tristate logiic is that the output pin has three states depending on how the internal source feeding it is connected.
1. High. When the pin is connected to the IC's +ve supply
2. Low. When the pin is connected to the IC's -ve supply
3. Open. When the pin is unconnected.
Irrespective of the output source, The logic level is '1' if the output pin is at V+, or '0' if at V-.
I don't share your understanding. Tristate gates have two (low impedace) states of output, that is 0 or 1. and one (high impedance) state of input, when the gate is "listening" to the signal. In the state of input the logic value will be defined by the circuit that is using the line to do its output. In your understanding all input pins existing in the world would also be tristate, since they can be connected to Vcc, to GND or not connected.

P.S.: Just for you to know, I'm new to this forum, not to electronics.
 

pebe

Joined Oct 11, 2004
628
You arleady told yourself the answer. Conducting = low impedance, cutoff = high impedance. Remember that a open swich does have a very high impedance (or resistance, its almost the same in this case), but it has. So a transistor will have too.
More to add, if a logic signal is 0 or 1, it depends on your vision. In false logic, 0 is +5V and 1 is 0 volts. In datasheets, the logic values are defined in terms of high and low, or in the case of open collector outputs, high impedance or low impedance. I am telling you this because open collector outputs are more often used in a false logic context, for example, if they are sinking current from LEDs.

I don't share your understanding. Tristate gates have two (low impedace) states of output, that is 0 or 1. and one (high impedance) state of input, when the gate is "listening" to the signal. In the state of input the logic value will be defined by the circuit that is using the line to do its output. In your understanding all input pins existing in the world would also be tristate, since they can be connected to Vcc, to GND or not connected.

P.S.: Just for you to know, I'm new to this forum, not to electronics.
I was refering to the output pins of ICs using tristate logic - not necessarily to gates.

Have a look at Motorola's data sheet for for the 74LS421. That explains my point.

P.S. I'm no stranger to electronics, either.
 

nomurphy

Joined Aug 8, 2005
567
A tri-state circuit is where the output consists of a push-pull configuration, it has complementary output transistors that will either drive the signal high or pull it low. However, when both output transistors are off, then the output is considered to be in a high-impedance state and effectively does not load the line or cause contention (such as "bus contention," where two or more drivers are trying to drive the same bus at the same time).

An open-collector or open-drain logic circuit is when there is NO internal output connection to the power supply Vcc or Vdd within the IC itself. It is dependent on the designer adding an external connection, usually a resistor of appropriate value, between the output and Vcc. This is to allow for wired-OR connections to a given line, such as an interrupt, that can be pulled low by multiple sources but cannot be driven high (hence the pull-up).
 

bloguetronica

Joined Apr 27, 2007
1,359
A tri-state circuit is where the output consists of a push-pull configuration, it has complementary output transistors that will either drive the signal high or pull it low. However, when both output transistors are off, then the output is considered to be in a high-impedance state and effectively does not load the line or cause contention (such as "bus contention," where two or more drivers are trying to drive the same bus at the same time).
Isn't that a topem pole output?

An open-collector or open-drain logic circuit is when there is NO internal output connection to the power supply Vcc or Vdd within the IC itself. It is dependent on the designer adding an external connection, usually a resistor of appropriate value, between the output and Vcc. This is to allow for wired-OR connections to a given line, such as an interrupt, that can be pulled low by multiple sources but cannot be driven high (hence the pull-up).
Exacly my point. That is why open collector outputs can only sink current (to ground). They cannot source current, and thus, their logic levels cannot be defined in terms of 0V or 5V. It depends on the external circuit whose imput is being sinked.
 

Ron H

Joined Apr 14, 2005
7,012
I don't share your understanding. Tristate gates have two (low impedace) states of output, that is 0 or 1. and one (high impedance) state of input, when the gate is "listening" to the signal. In the state of input the logic value will be defined by the circuit that is using the line to do its output. In your understanding all input pins existing in the world would also be tristate, since they can be connected to Vcc, to GND or not connected.

P.S.: Just for you to know, I'm new to this forum, not to electronics.
Not all tristate ports can "listen". The tristate pins on many parts are only outputs. Some do also have gates (inputs) connected internally to those pins.
 
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