I am trying to figure out why there is 2.55mA running through the drain of M1, it should not be there....also I noticed that I have a "gate" current which should not be there also....
I am using the The 50nm MOSFET models found at http://cmosedu.com/cmos1/cmosedu_models.txt
The currents out of the Source of M1 & M2 are negative, due to LTspice's definition, but they are flowing the correct way.
Does anybody know what I am doing wrong? Is their something wrong with my circuit design/DC Biasing?
I am using the The 50nm MOSFET models found at http://cmosedu.com/cmos1/cmosedu_models.txt
The currents out of the Source of M1 & M2 are negative, due to LTspice's definition, but they are flowing the correct way.
Does anybody know what I am doing wrong? Is their something wrong with my circuit design/DC Biasing?
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