# Dice oscillator

#### Wendy

Joined Mar 24, 2008
21,840
I'm looking for a oscillator that, when you press a button, oscillates fast (10Khz), then when you release the button it slows and comes to a stop. I know they are out there, I vaguely remember a UJT circuit that did something similar.

Ideas anyone?

#### SgtWookie

Joined Jul 17, 2007
22,201
Just for the fun of it, I whipped up the attached circuit.

The problem with using the VCO schematic by itself is that the output clock would never stop; it would just vary in frequency. I figured the easiest way to get it to stop would be to use a lower Vcc for the 555 timer than was used for the maximum CTRL voltage input.

This is accomplished by using a couple of 1N4148/1N914 diodes in series between the actual Vcc and the Vcc/8 and RST/4 pins. R3, a 10k resistor, provides a minimum current path through the diodes to ensure a voltage drop across them. This is necessary, as even though the standard 555 timer has an internal 5k/5k/5k divider, the CTRL input will be brought slightly higher than the 555 Vcc, which will effectively remove the voltage divider's load from the circuit.

Just to keep the simulation from taking forever to run (and making the plots more readable) I kept C1 rather large. Maximum frequency output is ~50Hz. Decreasing C1 to <= 10nF (0.01uF) would give an acceptably high frequency.

Not shown is the "roll" switch and resistor; LTSpice doesn't have a momentary switch and I didn't feel like making one. Point Q2b should be shorted to ground via a reasonably low-Ohm resistor; say 100 to 500 Ohms, just enough to keep from welding/pitting the switch contacts due to current flow from C3.

When power is turned on, C2 charges via D1 and D2. R3 limits the maximum Vcc due to the Vf of D1/D2. C3 starts off as discharged (or nearly so), and acts as a voltage follower of C3. R4 supplies the current to charge C3 over a ~1 second time period.

Initially, the clock output from the 555 timer runs at the typical astable rate, but as the voltage on C3 builds, the control voltage is raised so that it takes longer and longer for C1 to charge/discharge via the R1/R2 network, until finally the high threshold cannot be reached.

This circuit has not been tested on a breadboard, and is practically guaranteed to be "somewhat fiddly" as the UK'ers like to say. However, it's a starting place.

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#### djsfantasi

Joined Apr 11, 2010
5,475
I just happened to be reading "CMOS Cookbook" by Don Lancaster (2nd edition) and in Chapter 6 (I think) there is exactly the circuit that I believe you are looking for on pages 287-291. It is based on a VCO and a couple of flip flops to stop the oscillator once it has a chance to slow down.

If you are interested, I can attach a PDF of the circuit tomorrow?