Designing PCB that contains a SPI sensor

Thread Starter


Joined May 5, 2022
Hello everyone, first of all thank you for taking the time to give this a peak!

I am designing a PCB which is used as a HAT on a RaspberryPi and I am specifically designing it to use it for attaching a PMW3901 optical flow sensor.

I am unfamiliar with SPI sensors and have been googling around, which basically raised a question;

Am I supposed to add resistors on SPI tracks to reduce noise or is that overkill?

The distance between the connections and pathing on the PCB is less then 7 cm and would love to hear some advice on the topic.
After reading a lot of information online I am rather more confused then wise and have therefor turned to this forum.
Any assistance/insight is appreciated!


Joined Oct 2, 2009
SPI (Serial Peripheral Interface) is a synchronous clocked shift register protocol that is intended for inter-chip communication over short distances (200mm). Signals are typical TTL logic levels, 0-3V or 0-5V. Generally speaking, no additional resistors are required. (Check the datasheet of all devices using SPI.)


This is a Master-Slave protocol where the Master device sends MOSI, CLK, and /SS.
If there is only one slave device in your configuration, /SS input to the device can be wired to GND.


There are four control and data signals
MOSI - Master-Out Slave-In (data output from Master)
MISO - Master-In Slave-Out (data input to Master)
CLK - Clock (output from Master)
/SS - Slave Select (inverted) (output from Master if multiple slaves)

The Master generates the CLK signal, hence determining the transfer speed.
The Master also selects the polarity of the CLK, CPOL = 0 or 1, and which edge (phase) of the CLK is used (CPHA = 0 or 1).
Thus there are four options of CPOL and CPHA. The slave device must confirm with the selected option.

The number of clock pulses (and hence data bits) transferred in each transaction is determined by the application and devices.




Joined Oct 2, 2009
Layout of SPI is not critical if the CLK frequency is not very high and trace lengths are not too long.

The best protection you can provide is to use a GND flood plane around the data and control lines as I can see you have done.

Your PCB layout looks fine to me.