So I'm a programming student, but we have a computer architecture module. Just recently we started working with Proteus. Up to that point we had been discussing truth tables, binary conversions and k maps. So the jump to logic circuits was pretty fast.

So as part of our homework we were supposed to simplify truth table binary results to boolean algebra via k-map. Which I have done. But I'm completely lost how to do the actual multi-input gate implementation.

Basically there's two exercises:

1. Create a multi-input NAND gate implementation of the circuit with only NAND gates(for the expression).

2. Create a multi-input OR, AND and NOT gate implementation of the circuit for the expression.

My expression is : x = A’BCD’+AB’C’D+AB

Could you lead me the right path? There's 4 inputs going into a single output(A,B,C,D, right?). But how to i display that with OR AND and not gates? Or NAND gates?

 

Part 1.
How to do OR, AND and NOT gates using NAND gates: http://en.wikipedia.org/wiki/NAND_logic

 

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My expression is : x = A’BCD’+AB’C’D+AB

Could you lead me the right path? There's 4 inputs going into a single output(A,B,C,D, right?). But how to i display that with OR AND and not gates? Or NAND gates?

The basic approach is just to follow the expression.

Since the three ANDed functions are ORed together, a 3-input OR gate would be the last gate.

Then the first function has four functions ANDed so you need a 4-input AND gate for that. This AND gate output is one input of the above 3-input OR gate.

Two of the inputs to that AND gate are inverted so you need two inverters (NOT gates) for that.


Continue on with the second and third functons in the same manner until finished.

Make sense?

 

Thanks for all of the replies, I've already managed to do the second exercise with a bit of tinkering(I know it doesnt look amazing, but its just a first draft to see how it works):

Just have to figure out how to re-design that using NAND gates.

 

Okay so I've more or less figured out how to do the the whole thing with NAND Gates. My question is, if I want to replicate a 4 input AND gate, do I have to use two dual 4 input NAND gates, or do I use a single 4 input NAND gate and then connect it to a two input NAND gate and that would work?

P.S. Also, is there a big difference if the NAND gate is Dual 4-input?

 

I think its working...Looks messy as hell.

 

One important thing to note is that for negative logic, a NAND gate acts as a NOR gate (any input being low causes the output to go high). This can minimize the number of inverters required. For example if you use three four-input NAND gates to feed a three-input NAND GATE then the output is equivalent to the AND gates feeding the OR gate in your first design, no inverters between the gates required.

 

Okay quick question, how do you connect three input expressions with a 2 input and gates?

I did some recalculating and I had the whole thing wrong, my new expression is:

x = A’B+ABD’+AB’D

 

Okay quick question, how do you connect three inputs with a 2 input and gates?

Is there any functional difference between a*(b*c) and (a*b)*c?

 

Okay quick question, how do you connect three input expressions with a 2 input and gates?
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Are you limited to two-input gates?

 

Are you limited to two-input gates?

Yes I was, I figured it out anyway. You just need to add two and gates in a certain way.

 

Yes I was, I figured it out anyway. You just need to add two and gates in a certain way.

Yes, you add them with another AND gate.