Designing circuits for a latch using NAND Gates

Discussion in 'Homework Help' started by Jaden, Mar 28, 2010.

  1. Jaden

    Thread Starter New Member

    Mar 28, 2010
    Hello. I'm having trouble with part of this problem I'm working on.

    Part of it wants me to "Derive a circuit for the AB latch that has four 2-input NAND gates and 2 inverters". This is where I'm stuck at I have no idea how to do this.

    I also wanted to know if I got this right. In the first part it asked for us to make a state table and equation for AB as follows:

    A and B = 0, Q = 0
    A or B = 1, Q is unchanged
    A and B = 1, Q = 1

    A B Q+
    0 0 0
    0 1 Q
    1 0 Q
    1 1 1
    Q+ = BQ + AQ + AB

    So after a lot of trial and error this is the best I can come up with: [​IMG]
    Last edited: Mar 29, 2010
  2. dsp_redux

    Active Member

    Apr 11, 2009
    Looks like you got the first part right (the equation is ok for the table). I'll give you an hint for part two. Think about DeMorgan's law.
  3. Jaden

    Thread Starter New Member

    Mar 28, 2010
    Nevermind I figured out what DeMorgan's law was.
    Last edited: Mar 28, 2010