Hello, so my task is to design a 2 or 3 stage amplifier that has the following parameters:

Open-circuit (no-load) voltage gain: |​

 

Broodsliver, your BJT is improperly biased. I'll help you with this problem if you come back.

 

As already mentioned by PRS you BJT stage amp is not properly biased.
And your Ic current is much large then 0.626mA. Because your BJT is in saturation region.

 

First just want to apologize when I posted this on the computers at school, the requirements displayed values in case some cannot read them:

Open-circuit (no-load) voltage gain: |Avo|=100 (± 10%)
Number of transistors (stages): no more than 3;
• Power supply: +15V relative to the ground;
• Output resistance: 4.0 Komhs (±10%);
• Input resistance: no less than 50kohms;
• Maximum no-load output signal swing: 10V peak to peak (from −5V to +5V).


NPN Bipolar-Junction Transistor (BJT) 2N3904, β = 150,
VBE(on) = 0.7V Vcesat = 0.3 V

n-type enhancement MOSFET included in the chip ALD1106PBL
K=0.55 (mA/V^2), Vt=0.75

 

As already mentioned by PRS you BJT stage amp is not properly biased.
And your Ic current is much large then 0.626mA. Because your BJT is in saturation region.

Hmm okay. So i'm taking another look at it and I'm not quite sure where I should begin changing some values.

First question I have: Is what did correct in regards to the first stage, the resistor values correct? Next: I realize that I have a resistor in my Emitter so I that changes my gain correct? If Re was zero then the gain is just gmRc but since it's not, I suppose I have to take into account now.

Finally, does this actually work? I'm hoping by the fact it hasn't been blatantly said that is will not work that I am on the correct path

Thanks Jony130!

Broodsliver, your BJT is improperly biased. I'll help you with this problem if you come back.

I have seen your work around these forums while I was "Googling" things and stuff, your help is appreciated, although it seems your away atm, I'll be here untill I figure this out!

 

First just want to apologize when I posted this on the computers at school, the requirements displayed values in case some cannot read them:

Open-circuit (no-load) voltage gain: |Avo|=100 (± 10%)
Number of transistors (stages): no more than 3;
• Power supply: +15V relative to the ground;
• Output resistance: 4.0 Komhs (±10%);
• Input resistance: no less than 50kohms;
• Maximum no-load output signal swing: 10V peak to peak (from −5V to +5V).


NPN Bipolar-Junction Transistor (BJT) 2N3904, β = 150,
VBE(on) = 0.7V Vcesat = 0.3 V

n-type enhancement MOSFET included in the chip ALD1106PBL
K=0.55 (mA/V^2), Vt=0.75

Start with the output parameters. Exaggerate a little so that you design for 12 volts peak to peak at the collector. This gives you leeway when you use standard value resistors.

Rc needs to be greater than the spec due to its being in parallel with the transistor's output resistance of about 100k. So if you are using 5 percenters then use a 4.7k resistor there.

The signal will swing about a bias point, Vc. If we need +6 volts from there to the 15 volt rail, it follows Vc needs to be 15-6=9 volts.

To make this happen, what should the current, Ic, be? You can calculate this. Now what should Ve be in order for there to be a 6 volt swing across the CE junction? 9-6-Vcesat. So now you know Ve and Ie.

The gain is plenty to make the minimum spec.

You take it from here and I'll check back with you.

 

Thanks PRS!

So using Rc = 4.7k, 12vpp swing, Vc = 9[V] I find the following:

(15-9)/4.7 = 1.2765 [mA] = Ic
Ve = 9-6-0.3 = 2.7 [V]
Ie = ic/α = 1.2850 [mA]

Vbe = Vb - 2.7 --> Vb = 3.4[V]
Ib = 0.00851 [mA]

Now my problem is getting the Vb value after the resistor from Vcc.

I tried 2 ways:

15(r2/r1+r2)=3.4 solving this gives me a ratio of (17/58)R1 = R2

And 15 - RbIb = 3.4 ≈ 1.3Mohms

However I only have the resistors attached, and I'm unsure of which values to go for since they vary between what I should use via my calculations and what I actually have.

Thanks again!

 

Broodsliver, you got Ic and Ie right and notice they are about the same. And you got Ve right. The next step, knowing Ve and Ie is calculating Re=Ve*Re

Then knowing Ve we just add .7 volts to it and get Vb. From there do a voltage divider to get R1, start with R2=10*Re.

That will complete this exercise in futility. I have a shop in a room in my house and it was an easy matter to breadboard this circuit. With R1=100k, R2=22k, Re=2.2k, and Rc=4.7k, and with a 100uF cap across Re, I put a 1 kHz sine wave into the base through a coupling capacitor and read the output at Rc through a coupling capacitor and when I cranked up the input voltage at the base, to get a 10Vpp signal the output was distorted sine wave. Then I remembered something (it' been a while): you can't put more than 10mV into a common emitter amplifier without creating harmonic distortion. Staging doesn't help. You can partially bypass the emitter resistor but even then you can increase the input voltage only to about 100 mV.

There is not fix for this. Consider the fact that you need a 10 volt peak to peak signal at the output. This would force the gain to be 1000 volts per volt. This cannot be done. Let your instructor know this. He should rewrite the problem with this in mind.

Then I put a 22 ohm resistor between the emitter and Re to maintain the 100 v/v gain requirement while improving the shape of the output signal, but it didn't to the trick. I couldn't get a halfway decent looking output sine wave until I turned the input down to about 60mV and the output was 5 volts peak to peak. Notice the gain is only about 80? That's due to the harmonic distortion. Compression takes place. By the way the distortion causes the higher half of the signal to be fatter than the lower part.

At any rate you need to let your teacher know this problem is impossible to solve. And if he tells you otherwise, please let me know his solution!!!

 

To find voltage divider resistor simply use ohms law and KCL.
IR1 = (I2 + Ib) and normally we choose I2 = 10 *Ib
therefore R1 = (15V - 3.4V)(11 *8.51μA) = 124K and R2 = 3.4V/(10*8.51μA) = 39K. But you don't have 120K resistor.
So let as try different method.

Vcc/Vb = 1 + R1/R2 ---> R1 = (Vcc/Vb - 1 )*R2.

So is we assume R2 = 10KΩ --->R1 = 3.41*10K = 34k = 33KΩ
So we good with this.

But know you need to check your voltage gain.

 

This is an open ended lab design. We only have to build and show it to our professor if we wish to get some bonus mark, other wise I just need to do the simulations and have the "pre-lab" work to find the resistor/capacitor values and the stages to use.

Well it is unfortunate, I'm thinking of another way maybe using a CS,CC,then another CS amp. Maybe this will work better? Av1 10, Av2 close to 1 (hopefully at worst 0.9) then maybe 12 for the last gain.

Although it would be more work DC biasing the stages is it ultimately the better way to do things? Or should I not have a capacitor block the DC part from my 1st stage to 2nd stage and let the full AC signal and DC part flow and use that? Like wise from my 2nd to 3rd stage.

Appreciated

 

This is an open ended lab design. We only have to build and show it to our professor if we wish to get some bonus mark, other wise I just need to do the simulations and have the "pre-lab" work to find the resistor/capacitor values and the stages to use.

Well it is unfortunate, I'm thinking of another way maybe using a CS,CC,then another CS amp. Maybe this will work better? Av1 10, Av2 close to 1 (hopefully at worst 0.9) then maybe 12 for the last gain.

Although it would be more work DC biasing the stages is it ultimately the better way to do things? Or should I not have a capacitor block the DC part from my 1st stage to 2nd stage and let the full AC signal and DC part flow and use that? Like wise from my 2nd to 3rd stage.

Appreciated

Broodsilver, I think I may have found a way to get this done. Your idea of using the MOSFET in the follower mode is good. But the next stage, if it were a differential amplifier, might do the trick. Have you studied differential amplifiers yet? If so, this is what your instructor is looking for --- a FET follower feeding a differential amplifier. That's three transistors given that you use a resistor at the emitters of the differential amplifier. Also use the common mode design, not the single-ended design.

 

Broodsilver, I think I may have found a way to get this done. Your idea of using the MOSFET in the follower mode is good. But the next stage, if it were a differential amplifier, might do the trick. Have you studied differential amplifiers yet? If so, this is what your instructor is looking for --- a FET follower feeding a differential amplifier. That's three transistors given that you use a resistor at the emitters of the differential amplifier. Also use the common mode design, not the single-ended design.

Well he did learn in lecture about differential amplifiers, however I don't have any practice at solving their structures, nor do I yet know how they should be linked together (for symmetry), so far they have they just been MOSFET examples however, so I have no idea how their voltage gains should be calculated from a BJT differential amp, even as a base example. I'm guessing you mean BJT since you mentioned to use resistors in their emitters.

Also how to calculate it's output resistance.

 

Well he did learn in lecture about differential amplifiers, however I don't have any practice at solving their structures, nor do I yet know how they should be linked together (for symmetry), so far they have they just been MOSFET examples however, so I have no idea how their voltage gains should be calculated from a BJT differential amp, even as a base example. I'm guessing you mean BJT since you mentioned to use resistors in their emitters.

Also how to calculate it's output resistance.

I'll look into it and get back with you tomorrow. I used to be pretty good at this but I'm rusty and as they say use it or lose it. But do ask your instructor about the 10-100mV input verses his 10 V peak to peak output problem with respect to gain and make sure he is aware of it. If he is then that's good! It means there's a way to do this. I know there is a way using multiple stages with feedback, but I'm guessing this is not the case here.

 

Yesterday we and up with this circuit

With Ic = 1.2765mA and Ie = 1.285mA.
And we need Ve = 2.7V so
Re = 2.7V/1.285mA ≈ 2.2K

Now we need to take care of the voltage gain. Without Ce capacitor the gain is equal to
Av_without = Rc/Re = 4.7K/2.2K = 2.1V/V
So we need to decrease Re value for AC signals to increase the voltage gain. We can do this by adding Ce capacitor parallel with Re resistor.
This capacitor will short emitter to ground for AC signals. And thanks to this the gain increase to the new value:
Av = gm*Rc = Rc/re where
re ≈ 1/gm = 25mV/Ie = 19.5Ω
So our gain will reach new value
Av = 4.7KΩ/19.5Ω = 241V/V
But now our gain is way too high. So to fix this problem we need to add another resistor. But this time we need to add resistor in series with Ce capacitor. The value for this resistor can be find quite easy.
Rx = Rc/110 - 19.5 ≈ 22Ω
I use 110 instead of 100 because I want to compensate the gain drop in source follower.

 

Yesterday we and up with this circuit

With Ic = 1.2765mA and Ie = 1.285mA.
And we need Ve = 2.7V so
Re = 2.7V/1.285mA ≈ 2.2K

Now we need to take care of the voltage gain. Without Ce capacitor the gain is equal to
Av_without = Rc/Re = 4.7K/2.2K = 2.1V/V
So we need to decrease Re value for AC signals to increase the voltage gain. We can do this by adding Ce capacitor parallel with Re resistor.
This capacitor will short emitter to ground for AC signals. And thanks to this the gain increase to the new value:
Av = gm*Rc = Rc/re where
re ≈ 1/gm = 25mV/Ie = 19.5Ω
So our gain will reach new value
Av = 4.7KΩ/19.5Ω = 241V/V
But now our gain is way too high. So to fix this problem we need to add another resistor. But this time we need to add resistor in series with Ce capacitor. The value for this resistor can be find quite easy.
Rx = Rc/110 - 19.5 ≈ 22Ω
I use 110 instead of 100 because I want to compensate the gain drop in source follower.

Ohhh okay I see what you did. That actually helps me b/c I forgot to add in a couple of capacitors to thend of my CS's to increase the gain. But correct me if I'm wrong, If I wanted my output voltage signal swing to be 10V (± 5V) a CE amp can't do the job because it cant take in more than 10mVp-p?

I've stated on a new design a stage CS CD CS, and so far I've got gains of about 7,0.88, and 4. So I'm currently working on increasing 7 (my first CS stage) by at least 3, and my last CS stage by at least 5.

My problem is, when I put them together, staging them with capacitors I get a gain of about 1.02. So my question is, how does the signal work in passing through?

 

Also here is my schematic with all of them put together, and then with the first 2 stages and then the last 2 stages.

 

But correct me if I'm wrong, If I wanted my output voltage signal swing to be 10V (± 5V) a CE amp can't do the job because it cant take in more than 10mVp-p?

No, if the hole amplifier will have a voltage gain equal to 100V/V.
And you want Vout = 10Vp-p the Vin_max = 10/100 = 100mVp-p.
So what is your problem here?

My problem is, when I put them together, staging them with capacitors I get a gain of about 1.02. So my question is, how does the signal work in passing through?

Because you simply forget about the loading effect. Your first CS stage is loaded by CD stage input impedance.
Rin for CD stage is equal to 3.3K||1K = 0.77kΩ.
So the voltage gain of your firs stage will drop
Av = gm * (RD||Rin) ≈ gm*0.77K
And this is why your gain drops.

 

No, if the hole amplifier will have a voltage gain equal to 100V/V.
And you want Vout = 10Vp-p the Vin_max = 10/100 = 100mVp-p.
So what is your problem here?

PRS mentioned in a post yesterday that: "you can't put more than 10mV into a common emitter amplifier without creating harmonic distortion. Staging doesn't help. You can partially bypass the emitter resistor but even then you can increase the input voltage only to about 100 mV."

So if i can't put more than 10mVp-p into I can't get 100mV to get my 10Vp-p. Orrrr am I looking at this wrong?

Because you simply forget about the loading effect. Your first CS stage is loaded by CD stage input impedance.
Rin for CD stage is equal to 3.3K||1K = 0.77kΩ.
So the voltage gain of your firs stage will drop
Av = gm * (RD||Rin) ≈ gm*0.77K
And this is why your gain drops.

Ohhhh, well that makes things much more interesting. Hmm so, what are some steps I can take to help reduce my input impedances but still keep my overall gain or rather increase them from what I already have? If I change my Vg then I change my Vgs and following that the Vgs changes then so does Id and if that changes so does gm and ultimately Avo.

Should I be biasing my stages or should I be taking the outputs of the previous stage to the input of the next stage? I'm okay with doing the equations after repeating them so often, but with limited time I'm not sure which one will yield better results

 

This circuit works better than mine but still has a little distortion (the bottom part of a sine wave is more narrow than the top). This circuit is the same as mine except the voltage divider (R1 and R2). Your use of smaller resistors allows more current to flow into the base. Good job!

 

PRS mentioned in a post yesterday that: "you can't put more than 10mV into a common emitter amplifier without creating harmonic distortion. Staging doesn't help. You can partially bypass the emitter resistor but even then you can increase the input voltage only to about 100 mV."

So if i can't put more than 10mVp-p into I can't get 100mV to get my 10Vp-p. Orrrr am I looking at this wrong?

With the 22 ohm resistor in series with the emitter bypass capacitor 100mV is acceptable. Jony's circuit is probably good enough -- unless your instructor is worried about a little harmonic distortion. You'll do well to discuss the distortion problem in your report. By the way, I breadboarded Jony's circuit and even though the bottom portion is more narrow than the top I can't see doing any better than this with an emitter follower.

By using an R1 of 100k my design squeezed off the necessary current. Use Jony's design at your output but go back over my reasons for the 4.7K at Rc, 2.2K at Re and using the 22 ohm resistor in series with the bypass capacitor. Also, the necessary voltage at the base to get the necessary voltage at the emitter. Be sure to get a gain of at least one with your MOSFET (common drain) input stage.

I hope I've helped you. Good luck!