design for testability

Discussion in 'General Electronics Chat' started by vead, Jul 5, 2014.

  1. vead

    Thread Starter Well-Known Member

    Nov 24, 2011
    design for testability is process ensure that design has enough observability and controllability to provide for complete and efficient test

    test circuit is integrated to original circuit for purpose of testing

    Example - built in self test circuitry to original circuit
    - scan circuitry to original circuit

    built in self test - capability of circuit to test itself

    built in self test circuitry incorporated within chip for self testing

    test vector ---> original circuit & self test circuitry --> output response

    scan design - scan is technique used in design for testing

    test vector ---> original circuit & scan circuitry --> output response

    Q- how does test vector generate for built in self and scan design

    I think for scan we use ATPG to generate tset vector
    does we use ATPG for built in self test

    Q how does design make testable ?

    I think we add some flip flop and mux to make testable design

    Q can someone little bit how does circuit make controllable and observable
  2. ramancini8

    Active Member

    Jul 18, 2012
    The ultimate testable machine fits into either of two categories: first, there is a socket available that the test control cable plugs into (or an IC can be pulled to make a socket available), or second, the machine is so easy to disassemble that replacing parts is fast and simple.
  3. THE_RB

    AAC Fanatic!

    Feb 11, 2008
    Homework? :(
    vead likes this.
  4. MrCarlos

    Active Member

    Jan 2, 2010
  5. vead

    Thread Starter Well-Known Member

    Nov 24, 2011
    yes I am studying about VLSI testing

    this post only I have asked about testable design how does vlsi circuit make testable
  6. vead

    Thread Starter Well-Known Member

    Nov 24, 2011
    look at this post I asked question and given some option I don't want that someone explain in detail
  7. kubeek

    AAC Fanatic!

    Sep 20, 2005
  8. Brownout

    Well-Known Member

    Jan 10, 2012
    There are many many ways to generate test vectors, including Automatic Test Program Generation (ATPG)

    Scan cells, Boundary Scan cells and other special circuits or normal resources.