hello.
now i am doing my final year project.i'm working on design circuit to convert -1/+1 volt waveform of LTC to 0/+5 volt waveform.can anybody help me to design this cct. i try using level shifting but i can get the result when i do a simulation using multisim.

accually,i already design using 2.5 gain op amp and add a battery to to shift the level of voltage.but my friends said i will facing some problem if using battery.hope u all can help.

 

hello.
now i am doing my final year project.i'm working on design circuit to convert -1/+1 volt waveform of LTC to 0/+5 volt waveform.can anybody help me to design this cct. i try using level shifting but i can get the result when i do a simulation using multisim.

accually,i already design using 2.5 gain op amp and add a battery to to shift the level of voltage.but my friends said i will facing some problem if using battery.hope u all can help.

What is LTC?

 

LTC-linear time code.acctually i am was build a hardware that can log the packet in the network.and the packet must to be timestamp using LTC.unfotunetly LTC signal is -1 to 1 so i have to convert the signal to 0- 5 volt before i can timestamp the packet

 

Why not something like...

Parts List:
R1 - 10KΩ
R2,3 - 1KΩ
Q1,2 - 2N2222

2 transistor invertors back to back. The 1V signal should be enough to drive Q1, and it will ignore the -1V signal.

 

hello.
now i am doing my final year project.i'm working on design circuit to convert -1/+1 volt waveform of LTC to 0/+5 volt waveform.can anybody help me to design this cct. i try using level shifting but i can get the result when i do a simulation using multisim.

accually,i already design using 2.5 gain op amp and add a battery to to shift the level of voltage.but my friends said i will facing some problem if using battery.hope u all can help.

Well you were on the right track. What you need is a op amp circuit called a non inverting 2 input summer with a gain of 2.5.

Input #1 to the summer will be your signal +/- 1 vdc.
Input #2 to the summer will be a fixed 1 vdc potential supplied by a voltage divider (junction of two series resistors) wired to a regulated positive voltage source and circuit common, typically from the same voltage used for the + voltage needed by the op amp Vcc pin.

This fixed input voltage will force a 1 volt offset such that a -1 volt on the other summer input will cause a zero output on the op amp (-1 +1 = 0 X 2.5 = 0). Now if your signal goes to +1 then (+1 +1 = 2 X 2.5 = 5).

The negative voltage supply (Vdd pin) for the op amp should be a small negative voltage rather then circuit common as most op amps can't drive their output terminal equal to their negative (Vdd) voltage source and therefore cannot have a perfect zero volt output if their Vdd pin is only 0vdc.

Check out some common op amp data sheets and some should show examples of a summer circuit.

Good luck and stick to it, you will solve it

 

thanks..i will try to run your cct.actually i prefer to use op amp.and this is the desgn.the problem is when i try to simulate the have some error.i think the value of c1 and c2 and resistor is not suitable.can you help me?

 

thanks..i will try to run your cct.actually i prefer to use op amp.and this is the desgn.the problem is when i try to simulate the have some error.i think the value of c1 and c2 and resistor is not suitable.can you help me?

Well I would use a true summer circuit as shown in this link. They show a 3 input summer with a gain of 3 so you will have to eliminate one of the summer resistors, recalculate the gain resistors to 2.5 and finally wire a voltage divider string to one of the summer inputs.

http://www.allaboutcircuits.com/vol_3/chpt_8/8.html

 

Here's another way you could do it using a comparator. See the attached.

The 78L05 regulator is there in case you want to run from a 7v or higher battery.

R1 and R2 are a summer circuit, raising the average input voltage to 2.5v.

R3 sets the comparator trigger level. R4 provides hysteresis. Comparators generally have open-collector outputs, R5 provides a current source; when the comparator output is ON, R5 will be passing about 2.8mA.

An NPN transistor & resistor could be added to the output if more current is desired. Swap the connections to the inverting and noninverting inputs of the comparator if you want the polarity of the output signal to match the input signal.

If you have unused comparators in the IC you select, tie the noninverting inputs to ground and the inverting inputs to Vcc, or vice versa; this will prevent them from randomly oscillating.

 

Why not something like...

Parts List:
R1 - 10KΩ
R2,3 - 1KΩ
Q1,2 - 2N2222

2 transistor invertors back to back. The 1V signal should be enough to drive Q1, and it will ignore the -1V signal.

Change R2 to 10k and it should work. The rule of thumb for forced beta for a saturated BJT is Ic/Ib≈10. With the values you listed, Ic1/Ib1≈125(!), and Ic2/Ib2≈1.16. Changing R2 to 10k yields Ic1/Ib1≈12.5, and Ic2/Ib2≈11.6, which should ensure good saturation of both transistors.