hi guys, i need some help in my Electronics Lab project.

The project is as follows:

Design an Amplifier that meets a set of specifications:

1. |Av|=10 plus minus 2
2. Rin>=50 kohm
3. Ro<=50 ohm
4.Q point is stable within plus minus 10%
5.Vo is not distorted
6.Fl<=20Hz
7.Fh>=100kHz

avaialbe resistors:
100,220,330,390,470,680,820 ohm
1,2.2,3.9,4.7,6.8,8.2 kohm
10,22,39,68,82,100,220,470 kohm
1 mohm
0.1,0.68 microF
Vcc=15V

Vs=0.1sinwt , Rs = 50ohm
RL=2.2 kohm

using NPN BJT (BC 107) transisstors.


My solution:

judging from Ro<=50 ohm, we need 2 stage amp , one is Common Emiiter for the gain, and another is common collector for the buffer.

i came up with a design, unfortunately , i cant tell if its correct or not, so all im asking if anyone can check it for me, and to coorect anything wrong with my design.

 

I think you should go to http://www.linear.com and download the excellent, free LTspice circuit simulator. YOu can use it to find all of the answers, about your circuit, and make changes and see the results, etc. It's extremely easy to use.

- Tom Gootee

http://www.fullnet.com/~tomg/index.html

 

You might need another gain stage.

Also, with the two stages you have now, you would at least need to increase the 1K emitter resistor (R5) to 3.6k or more, just to avoid massive distortion.

And the lower end of your bandwidth is at about 700 Hz. Hint: Calculate the cutoff frequencies for the high-pass filters formed by C2, R7 and C1, R3.

- Tom Gootee

http://www.fullnet.com/~tomg/index.html

 

I simulated it with LTSpice. Its input is biased wrong so it clips the bottom of the signal. By increasing R2 from 220k to 1M (1000k) then it is biased correctly.

 

I simulated it with LTSpice. Its input is biased wrong so it clips the bottom of the signal. By increasing R2 from 220k to 1M (1000k) then it is biased correctly.

DOH! OK, that works.

I did notice that replacing the 1Meg with a series combo of 470k, 220k, and 39k reduces the distortion (THD @ 20 kHz) from 0.173% to 0.0182%. (That was with 0.68uF caps for both input and output.)

With two stages, I don't see how he can get an f3dB_low of 20 Hz without paralleling six of the 0.68 uF caps, at the output.

Also, it looks like the output impedance is above 50 Ohms until f >= 8 kHz or so. And even with 6x || 0.68uF for the output cap, it's still above 50 Ohms until about 1.3 kHz.

- Tom Gootee

http://www.fullnet.com/~tomg/index.html