Design an 8-to-1 MUX using a 3-to-8 decoder and AND gates and one OR gate.

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Anony1234

Joined Oct 28, 2013
2
This isn't homework, but it is a question I have had since the beginning of the semester.

I did this by putting each output of the 3-to-8 decoder going into a 2-input AND gate, each of which has an input I0 thru I7 going into it as well, and then connecting all of these to an OR gate at the end.

This is meant to simulate the multiplexer equation of: output Z=I0S0'S1'S2' + ... + I7S0S1S2.

However, I kind of didn't answer the question correctly because I used those additional inputs into the AND gates, of I0 thru I7. It isn't specified whether this is allowed (it seems not to be the way the question is phrased), but I couldn't think of any way to do it otherwise.

Is there any way to do this other than the way that I specified?
 

WBahn

Joined Mar 31, 2012
29,930
Sounds fine. In practice you would use eight 2-input NAND gates and one 8-input NAND gate plus the 3:8 decoder.

Since the output HAS to depend on I0 through I7, you had to use them at some point.
 

absf

Joined Dec 29, 2010
1,968
This isn't homework, but it is a question I have had since the beginning of the semester.

I did this by putting each output of the 3-to-8 decoder going into a 2-input AND gate, each of which has an input I0 thru I7 going into it as well, and then connecting all of these to an OR gate at the end.

However, I kind of didn't answer the question correctly because I used those additional inputs into the AND gates, of I0 thru I7. It isn't specified whether this is allowed (it seems not to be the way the question is phrased), but I couldn't think of any way to do it otherwise.

Is there any way to do this other than the way that I specified?
If you must use 8x AND gates to design your MUX, then you'd have to invert the inputs before entering the AND gates. The 8-input OR gate also has to be replaced with a NOR gate to invert the input back, so the output would be correct. See the attached schematic for reference.

It would be more elegant to design with NAND gates as suggested by WBahn...:)

Allen
 

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WBahn

Joined Mar 31, 2012
29,930
If you must use 8x AND gates to design your MUX, then you'd have to invert the inputs before entering the AND gates. The 8-input OR gate also has to be replaced with a NOR gate to invert the input back, so the output would be correct. See the attached schematic for reference.

It would be more elegant to design with NAND gates as suggested by WBahn...:)

Allen
I think a generic 3:8 Decoder (i.e., no specific part number) would be an active-HI output (i.e., only the decoded line is HI, the rest are LO).
 

absf

Joined Dec 29, 2010
1,968
I think a generic 3:8 Decoder (i.e., no specific part number) would be an active-HI output (i.e., only the decoded line is HI, the rest are LO).
I think so. But 74138 is more commonly used than 74238 in real life.

Allen
 

WBahn

Joined Mar 31, 2012
29,930
I think so. But 74138 is more commonly used than 74238 in real life.

Allen
But we aren't talking real life. It appears to me that he is working with generic paper-only logic constructs and not a family of logic parts at all.
 

Danm1

Joined Jul 19, 2010
69
A lot of the 7400 series logic was used is collage course work, but has steadily been used less in actual products if the complex combinational logic can be put in FPGAs and CPLDs etc.
 

WBahn

Joined Mar 31, 2012
29,930
That may be. But nothing the OP has said indicates one way or the other what is being used, if anything. This may be a simulated design or it may be a purely paper/pencil design using generic, conceptual logic blocks. The latter seems the more likely at this point. Only the OP can clear this point up.
 
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