This isn't homework, but it is a question I have had since the beginning of the semester.
I did this by putting each output of the 3-to-8 decoder going into a 2-input AND gate, each of which has an input I0 thru I7 going into it as well, and then connecting all of these to an OR gate at the end.
This is meant to simulate the multiplexer equation of: output Z=I0S0'S1'S2' + ... + I7S0S1S2.
However, I kind of didn't answer the question correctly because I used those additional inputs into the AND gates, of I0 thru I7. It isn't specified whether this is allowed (it seems not to be the way the question is phrased), but I couldn't think of any way to do it otherwise.
Is there any way to do this other than the way that I specified?
I did this by putting each output of the 3-to-8 decoder going into a 2-input AND gate, each of which has an input I0 thru I7 going into it as well, and then connecting all of these to an OR gate at the end.
This is meant to simulate the multiplexer equation of: output Z=I0S0'S1'S2' + ... + I7S0S1S2.
However, I kind of didn't answer the question correctly because I used those additional inputs into the AND gates, of I0 thru I7. It isn't specified whether this is allowed (it seems not to be the way the question is phrased), but I couldn't think of any way to do it otherwise.
Is there any way to do this other than the way that I specified?