design a vhdl code for 2-way set associative cache

Discussion in 'Homework Help' started by GipsyDanger, Dec 12, 2013.

  1. GipsyDanger

    Thread Starter New Member

    Dec 12, 2013
    hello there

    i has an assignment due to 1 week later, but until now seems i can't understand the meaning of the problem given by my teacher

    the problem is:

    design a vhdl code for 2 -ways associative cache
    * 16 bit adress
    * 8 set
    * 8 byte block
    * random replacement
    * output hit/miss

    please someone share some references that i can learn , or vhdl code so i can understand.


    best regards
  2. WBahn


    Mar 31, 2012
    There are plenty of resources on line to explain the concepts behind set-associative caches. Start by trying to draw a map of the cache and by identifying what parts of the address map to the different pieces, such as the index, the tag, and the offset.

    Also, you need to be clear on the memory organization. In particular, how wide are the words and is the 16-bit address the byte address or the word address?

    Finally, you need to provide YOUR best efforts to work YOUR homework problem. That will give us the starting point we need to help guide you toward a solution.