Delay logic state change

I want to develop a relatively simple, low latency (under 40ns) TTL level circuit that will…

Have the output follow the input level, with low latency (under 40ns) except once the output goes high, it needs to stay high for at least 40ns.

In other words with more detail:
Circuit Input: high speed comparator output pulses that widely vary in duration and time between pulses (few ns to ms)(not PWM)
Output: to be low when input is low and high when input pulses are high, but only fall when both the input is low and there has been at least 40ns of duration after output rose. Output going to an IC that says it expects a “minimum input on-time of 40ns”, but I don’t want it much longer than 40ns if the comparator output has already dropped low.

Is there a name for such a circuit/need? As a relative newbie, I’m pretty much at a loss on where to start. I’ve read and have experimented with some latches, but don’t know how to incorporate the 40ns need. Can you at least point me in the right direction?

Comparator not yet chosen and considering TLV3201, or MCP6561 or MCP6566 (in that order), but the data sheets don’t tell me what the output pulses look like if the input switches past the comparator’s hysteresis faster than 20MHz. To model the TI comparator, it seems like I need to acquire/learn TINA-TI. At least the others have regular SPICE models that I can probably figure out how to get into Multisim. And then I wonder about believing the models at those high frequencies. I may just need to buy & breadboard the comparator to check it out. …But I still figure I’ll need the circuit described above.