Delay exists when No Prescaler

Discussion in 'Embedded Systems and Microcontrollers' started by micropad, Feb 2, 2012.

  1. micropad

    Thread Starter Active Member

    Dec 24, 2011
    Dear All
    As per attached picture timer1 increment delay exists when No Prescaler 0.5TCY + 20 at High Pulse Width but with With Prescaler is 10ns
    please explain how this happen
  2. kubeek


    Sep 20, 2005
    How are we supposed to know what the hell you´re talking about?
    Maybe post the type and brand of the thing you´re looking at...
  3. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    These are specs for the Timer 0 module of a Microchip controller. The baseline devices all look and work very similarly.

    That is not a "delay" but the minimum pulse widths and rates you can use to drive the timer, and is only a concern when you are using an external clock source. It is always OK to use the internal clock source.

    Tcy is the instruction rate of 4÷clock. You don't state your clock so I will assume an 8MHz source for a Tcy of 0.5uS. For no prescaler (Param No.'s 40 & 41) this gives a pulse width of 0.5*0.5uS + 20 nS, or 255nS. When using the prescaler the width is a fixed 10nS, which is rather fast.

    However, the period rate (Param No. 42) is still much larger. For the 8MHz clock here are the required periods:

    Code ( (Unknown Language)):
    2. N (prescale)  Min Period (uS)
    3.     1           540
    4.     2           270
    5.     4           135
    6.     8            67.5
    7.     16           33.8
    8.     32           16.9  (use min of 20)
    9.     64            8.4  (use min of 20)
    10.     128           4.2  (use min of 20)
    11.     256           2.1  (use min of 20)
    So the clock doesn't need to be a square wave, but the period needs to be large enough to ripple thru.

    (joeyd99, are you out there? Do you check this?)
  4. John P

    AAC Fanatic!

    Oct 14, 2008

    nsec not usec!

    It says T0CKI Period is Greater of:
    20 or (TCY + 40)/N

    where N is prescale factor, so worst case is when N = 1, and for a .5usec Tcy that does indeed give 540nsec. But the units do matter!

    Actually N=1 is covered as "no prescaler", and it works out the same, but you have to consider time high and low. For the maximum rate, you'd end up with a symmetrical clock, 0.5Tcy + 20, high and low.
    ErnieM likes this.
  5. ErnieM

    AAC Fanatic!

    Apr 24, 2011
    Corrected table:

    Code ( (Unknown Language)):
    1. N (prescale)  Min Period [B](nS)[/B]
    2.     1           540
    3.     2           270
    4.     4           135
    5.     8            67.5
    6.     16           33.8
    7.     32           16.9  (use min of 20)
    8.     64            8.4  (use min of 20)
    9.     128           4.2  (use min of 20)
    10.     256           2.1  (use min of 20)
  6. John P

    AAC Fanatic!

    Oct 14, 2008
    To refer back to the original question, I think the issue was why the specs seem to demand a slower clock rate when the prescaler isn't in use, versus when it is used. The reason for this has to be that once it's set up, the prescaler functions as independent hardware that reduces the clock rate fed to the actual counter, and it also ensures that the counter receives a true square wave. The prescaler can be fed narrow pulses, down to 10nsec in width, but the counter has stricter requirements, because it needs to synchronize its operation with the timing of the processor. Hence there's a timing requirement for the timer--but not the prescaler--that refers to processor clock speed.