# delay a signal by 3/4 clock period

Discussion in 'Homework Help' started by induv, Apr 15, 2013.

1. ### induv Thread Starter New Member

Apr 15, 2013
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0
I need to design a circuit to delay a signal by 3/4 clock period. I know by using flip-flops we can design a circuit to delay by 1/2, 1/4, 1/8...clock period but how to delay signal by 3/4 clock period. Can anyone please help me in designing this circuit?

Thanks a lot!

2. ### Jony130 AAC Fanatic!

Feb 17, 2009
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Are you sure that you want a delay circuit? Not a frequency divider?

Last edited: Apr 15, 2013
3. ### WBahn Moderator

Mar 31, 2012
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Okay, so let's start with what you say you already know. How would you design a circuit to delay by 1/4 clock period?

4. ### induv Thread Starter New Member

Apr 15, 2013
2
0
my bad, the one that I know is frequency divider circuit. Now I want to design a delay circuit that delays the incoming signal by 3/4 and 1/2. For example lets say that the incoming signal is 100 mbps and the delay circuit should delay the signal by 1/2 and 3/4 i.e. 5 ns and 7.5 ns respectively. Please help me with this design.

Thanks a lot.

5. ### WBahn Moderator

Mar 31, 2012
22,879
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Do you know about frequency doublers?

6. ### absf Senior Member

Dec 29, 2010
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Using an XOR gate you can easily double the incoming clock frequency. If you use PLL techniques, you can triple or 4 times the input frequency.

See schematic attached.

Allen

• ###### 7486 freq doubler.PNG
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Last edited: Apr 17, 2013
7. ### WBahn Moderator

Mar 31, 2012
22,879
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I'm not too fond of the waveform at the output of the XOR. I know you are using two Schmitt-trigger inverters to clean it up, which is probably good enough.

What if you put a Schmitt-trigger inverter after the RC delay and before the input to the XOR? You should be able to move one of the inverters from after the circuit and get the same output you have now.

absf likes this.