Definition of Tristated

Discussion in 'General Electronics Chat' started by Joster, Oct 27, 2013.

  1. Joster

    Thread Starter Member

    Jun 12, 2013
    Can anyone tell me what "Tristated" means here?


    EEPROMs have 3 control pins : CE (Chip Enable) , WE (Write Enable) , OE (Output Enable)
    This truth table should make it pretty clear how the 3 pins work :
    CEOEWEIC Status000Invalid Condition001Read Mode010Write Mode011Outputs are Tristated100Chip Disabled – Outputs are Tristated101Chip Disabled – Outputs are Tristated110Chip Disabled – Outputs are Tristated111Chip Disabled – Outputs are Tristated
  2. Jony130

    AAC Fanatic!

    Feb 17, 2009
  3. ian field

    AAC Fanatic!

    Oct 27, 2012
    Tri-state means exactly that, there are 3 output states; logic high, logic low and high impedance - which another device on the same bus can drive the lines without conflict.

    "Tri-stated" is a colloquial term that refers to the third state - high impedance output so another device can control the bus lines.
  4. ScottWang


    Aug 23, 2012
    To check 74LS125 or 74LS126 from TI, they provided the internal structure of the IC.

    Input the logic voltage from the data input(0,1) and also input the logic voltage(0,1) from the control input, and to see what will happen to the output pin.
  5. ian field

    AAC Fanatic!

    Oct 27, 2012
    On many devices OE is active low (always check datasheet) if you have 2 identical static RAM or 2 ROM chips and want to switch between them, wire all memory bus in parallel (A0 to A0, A1 to A1 and so on) do the same with the data bus lines. You have a single select line that can be high or low, wire that to the OE pin on one of the chips, then connect the input of an inverter to that OE pin and take the inverter output to the OE pin on the other chip.

    Regardless the state of the select line - only one of the chips has the active sense on the OE pin, that means that only one of the chips has active data bus outputs - the other one is "tristated" or high impedance, so doesn't interfere with the data put on the bus by the other chip.

    Its common to do this with multiple chips using an active low 1 of n decoder (so the " device address" is a binary number before decoding), you often find 4, 8 or 16 devices paralleled on a data bus where only 1 is selected at a time.
    absf likes this.