Hi, I'm new to verilog; I have been doing circuit design for years.
My problem is this:
I have a design, with an input bus to it, but the bus is non continuous. Let's say the bus is called "a" and I'd like to have bits 1 and 8 of the bus as primary inputs to my design, the others bits don't exist in the design. How do I define this in verilog?
Once I write the verilog, I send it off to a tool to try and construct a schematic from it, but the tool complains about incoming verilog format. I tried the following combinations but they did not work.
module <design> ... a ...
~
input [1] a;
input [8] a;
~
=========
module <design> ... a ...
~
input [1,8] a;
~
=========
module <design> ... \a[8] \a[1] ...
~
input \a[8] ;
input \a[1] ;
~
Here port name is preserved as a literal, but I don't want this. I want verilog to understand that this is a bus, and not a string.
=========
Please advice.
Thanks...
My problem is this:
I have a design, with an input bus to it, but the bus is non continuous. Let's say the bus is called "a" and I'd like to have bits 1 and 8 of the bus as primary inputs to my design, the others bits don't exist in the design. How do I define this in verilog?
Once I write the verilog, I send it off to a tool to try and construct a schematic from it, but the tool complains about incoming verilog format. I tried the following combinations but they did not work.
module <design> ... a ...
~
input [1] a;
input [8] a;
~
=========
module <design> ... a ...
~
input [1,8] a;
~
=========
module <design> ... \a[8] \a[1] ...
~
input \a[8] ;
input \a[1] ;
~
Here port name is preserved as a literal, but I don't want this. I want verilog to understand that this is a bus, and not a string.
=========
Please advice.
Thanks...