Hi all,
I am programming an MCP4821 DAC using SW_SPI on my PIC18F2550 and have had virtually no issues with setting the output voltage, except for the odd Power-on-Reset.
The reference voltage of the DAC is 2.048V and the values that I am trying to set it for are between 100mV and 300mV. The issue that I am noticing is that every now and then the first write to DAC after a POR causes an output voltage roughly equal to the reference voltage (2.048V). Subsequent writes alleviate the issue and operation is as expected, but I'm not 100% sure what is happening as this does not occur on every POR.
From Page 16 in the datasheet:
The Power-On Reset (POR) circuit ensures that the DACs power-up with SHDN = 0 (high-impedance). The devices will continue to have a high-impedance output until a valid Write command is performed to either of the DAC registers and the LDAC pin meets the input low threshold. If the power supply voltage is less than the POR threshold (Vpor = 2.0V, typical), the DACs will be held in their reset state. They will remain in that state until Vdd > Vpor and a subsequent Write command is received.
I have a 1uF cap on the output, 0.1uF cap on the supply pin, and LDAC tied low as per the datasheets suggestions.
I have single-triggered the first SPI write sequence of bits and it matches with what is expected. I have no idea how the output would be set to ~2V as the bit sequence would have to be pretty different.
Wondering if anyone has experienced this or has any idea on what might be happening.
Thank you.
I am programming an MCP4821 DAC using SW_SPI on my PIC18F2550 and have had virtually no issues with setting the output voltage, except for the odd Power-on-Reset.
The reference voltage of the DAC is 2.048V and the values that I am trying to set it for are between 100mV and 300mV. The issue that I am noticing is that every now and then the first write to DAC after a POR causes an output voltage roughly equal to the reference voltage (2.048V). Subsequent writes alleviate the issue and operation is as expected, but I'm not 100% sure what is happening as this does not occur on every POR.
From Page 16 in the datasheet:
The Power-On Reset (POR) circuit ensures that the DACs power-up with SHDN = 0 (high-impedance). The devices will continue to have a high-impedance output until a valid Write command is performed to either of the DAC registers and the LDAC pin meets the input low threshold. If the power supply voltage is less than the POR threshold (Vpor = 2.0V, typical), the DACs will be held in their reset state. They will remain in that state until Vdd > Vpor and a subsequent Write command is received.
I have a 1uF cap on the output, 0.1uF cap on the supply pin, and LDAC tied low as per the datasheets suggestions.
I have single-triggered the first SPI write sequence of bits and it matches with what is expected. I have no idea how the output would be set to ~2V as the bit sequence would have to be pretty different.
Wondering if anyone has experienced this or has any idea on what might be happening.
Thank you.