# D-latch & D-flip flop

#### nanobyte

Joined May 26, 2004
120
What is the difference between a D-latch and a D-flip flop? Both seem to be doing the same thing; Q follows D.

#### Dave

Joined Nov 17, 2003
6,969
Flip-flops are edge triggered, i.e. the output Q will only follow D at the edge of the clock; whether it be rising or falling edge is dependant on the flip flop design.

Latches are transparent in the enable configuration, i.e. if the latch is enabled the output Q will follow the input D for all changes in D - there is no requirement for an clock edge like for a flip-flop.

#### isha

Joined Sep 16, 2005
36
Originally posted by nanobyte@Oct 28 2005, 12:56 PM
What is the difference between a D-latch and a D-flip flop? Both seem to be doing the same thing; Q follows D.
[post=11317]Quoted post[/post]​
i think both are same
bcuz they do the same job

#### Dave

Joined Nov 17, 2003
6,969
Originally posted by isha@Oct 30 2005, 05:15 AM
i think both are same
bcuz they do the same job
[post=11354]Quoted post[/post]​
Read my post above, they certainly don't do the same things. Flip-flops require clock edges, where as latches only require enabling or disabling. If you consider the output of flip-flops and latches for the same inputs and clock cycle (where for a latch the clock goes to the enable input), you will find that the outputs will be different.

Look at the attached diagram showing the output of the latch QL and output if the flip-flop QFF for the same inputs and clock cycle. (Note: In this example the latch is enable-high and the flip-flop is rising edge triggered).

[attachmentid=933]

#### JoeJester

Joined Apr 26, 2005
4,390

#### nanobyte

Joined May 26, 2004
120
What's up everybody. Umm Dave, how come in your diagram the Q output for the flip flop is flat. Shouldn't it have some pulses in response to the clock edges (rising or trailing - which ever one it is suppose to respond to)?

#### Dave

Joined Nov 17, 2003
6,969
Originally posted by nanobyte@Oct 30 2005, 10:11 PM
What's up everybody.  Umm Dave, how come in your diagram the Q output for the flip flop is flat.  Shouldn't it have some pulses in response to the clock edges (rising or trailing - which ever one it is suppose to respond to)?
[post=11365]Quoted post[/post]​
Remember for the flip-flop the input D is latched to the output Q only on the rising edge of the clock. If you look at the diagram, for all rising edges of the clock the input D is low therefore the output Q never changes. (Note, for clarity I have ignored any delays in the timing diagram).

I have noticed a small error is the output for the latch QL. After the last risng edge of the clock (rising edge number 3) the output QL should go temporarily low, until the input D goes high. Apologies for the mistake.

Attached is a correction:

#### blahgod

Joined Nov 1, 2005
1
for d FF: d=q on time of clk, @ NGT or PGT depending on the device

#### webcrawler

Joined Jun 15, 2016
1
Flip-flops are edge triggered, i.e. the output Q will only follow D at the edge of the clock; whether it be rising or falling edge is dependant on the flip flop design.

Latches are transparent in the enable configuration, i.e. if the latch is enabled the output Q will follow the input D for all changes in D - there is no requirement for an clock edge like for a flip-flop.
Why do they sometimes referred to D-flip flop as latch

#### crutschow

Joined Mar 14, 2008
34,389

Flip-flops are sometimes called latches because technically they are edge-triggered latches.

(Welcome to the Forum.
It's a standing joke here that many first time posters bring back very old posts to comment on.
In this case you've brought back one that's over 10 years old.)

#### Techno Tronix

Joined Jan 10, 2015
139
In D-latch the output can changes according to the input where in D-flip-flop the output only changes according to the control signal from up to down or down to up.

#### hp1729

Joined Nov 23, 2015
2,304
Flip-flops are edge triggered, i.e. the output Q will only follow D at the edge of the clock; whether it be rising or falling edge is dependant on the flip flop design.

Latches are transparent in the enable configuration, i.e. if the latch is enabled the output Q will follow the input D for all changes in D - there is no requirement for an clock edge like for a flip-flop.
Authors and manufacturers may differ but I like Dave's definitions.

#### WBahn

Joined Mar 31, 2012
30,012
There's no hard and fast definition -- otherwise terms like "transparent latch" would be redundant while "edge-triggered latch" would be a contradiction in terms -- and some authors make no distinction between them at all, but rather use qualifiers (such as "transparent", "level-triggered", and "edge-triggered") to describe the key behavior; so you need to look at the data sheet for the particular devices you are considering to determine their behavior. If you don't and just assume that the device manufacturer is using the terms the same you are used to seeing them, then sooner or later you will get burned. Having said that, probably most people that make a distinction follow Dave's descriptions -- latches are level-triggered while flip-flops are edge-triggered.